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M37754S4CHP Datasheet(PDF) 11 Page - Mitsubishi Electric Semiconductor |
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M37754S4CHP Datasheet(HTML) 11 Page - Mitsubishi Electric Semiconductor |
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11 / 114 page  11 MITSUBISHI MICROCOMPUTERS M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 5. Index register length flag (x) The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is “0” and as 8- bit registers when it is “1”. This flag can be set and reset with the SEP and CLP instructions. 6. Data length flag (m) The data length flag determines whether the data length is 16-bit or 8-bit. The data length is 16-bit when flag m is “0” and 8-bit when it is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions. 7. Overflow flag (V) The overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. If data length flag m is “0”, the overflow flag is set when the result of addition or subtrac- tion is outside the range between –32768 and +32767. If data length flag m is “1”, the overflow flag is set when the result of addition or subtraction is outside the range between –128 and +127. It is reset in all other cases. The overflow flag can also be set and reset directly with the SEP, and CLV or CLP instructions. Additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of –2147483648 to +2147483647 in the RMPA operation. 8. Negative flag (N) The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag m is “0”, data’s bit 15 is “1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other cases. It can also be set and reset with the SEP and CLP instruc- tions. 9. Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of 3 bits and de- termines the priority of processor interrupts from level 0 to level 7. Interrupt is enabled when the interrupt priority of the device request- ing interrupt (set using the interrupt control register) is higher than the processor interrupt priority. When interrupt is enabled, the current processor interrupt priority level is saved in a stack and the proces- sor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details. Note: Fix bits 11 to 15 of the processor status register (PS) to “0”. BUS INTERFACE UNIT The CPU operates on the basis of internal clock φ CPU frequency. In order to speed-up processing, a bus interface unit is used to pre- fetch instructions when the data bus is idle. The bus interface unit synchronizes the CPU and the bus and pre-fetches instructions. Fig- ure 4 shows the relationship between the CPU and the bus interface unit. The bus interface unit controls buses to access memories easily. Refer to BUS CYCLE on the following pages. The bus interface unit has a program address register, a 3-byte instruction queue buffer, a data address register, and a 2-byte data buffer. The bus interface unit obtains an instruction code from memory and stores it in the instruction queue buffer, obtains data from memory and stores it in the data buffer, or writes the data form the data buffer to the memory. Fig. 4 Relationship between the CPU and the bus interface unit D'8–D'15 CPU Bus interface unit A'0–A'23 Control signal D'0–D'7 D8–D15 A0–A23 BHE ALE BYTE HOLD RD WR D0–D7 |
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