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MAX5594EUG Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX5594EUG Datasheet(HTML) 8 Page - Maxim Integrated Products |
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8 / 33 page  Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs 8 _______________________________________________________________________________________ TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) (DVDD = 2.7V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Frequency fSCLK 2.7V < DVDD < 5.25V 20 MHz SCLK Pulse-Width High tCH (Note 7) 20 ns SCLK Pulse-Width Low tCL (Note 7) 20 ns CS Fall to SCLK Fall Setup Time tCSS 10 ns DSP Fall to SCLK Fall Setup Time tDSS 10 ns SCLK Fall to CS Rise Hold Time tCSH 5ns SCLK Fall to CS Fall Delay tCS0 10 ns SCLK Fall to DSP Fall Delay tDS0 10 ns DIN to SCLK Fall Setup Time tDS 12 ns DIN to SCLK Fall Hold Time tDH 5ns SCLK Rise to DOUT_ Valid Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode 30 ns SCLK Fall to DOUT_ Valid Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 mode 30 ns CS Rise to SCLK Fall Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 10 ns CS Pulse-Width High tCSW 45 ns DSP Pulse-Width High tDSW 20 ns DSP Pulse-Width Low tDSPWL (Note 8) 20 ns UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance 100 ns DOUTRB Tri-State Time from CS Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_ in high impedance 20 ns DOUTRB Tri-State Enable Time from 8th SCLK Fall tZEN CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state 20 ns LDAC Pulse-Width Low tLDL Figure 5 20 ns LDAC Effective Delay tLDS Figure 6 100 ns CLR, MID, SET Pulse-Width Low tCMS Figure 5 20 ns GPO Output Settling Time tGP Figure 6 100 ns GPO Output High-Impedance Time tGPZ 100 ns |
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Similar Description - MAX5594EUG |
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