GS8182S08/09/18/36BD-400/375/333/300/250/200/167

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.03c 11/2011

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© 2007, GSI Technology

protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at

the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write

addresses like SigmaCIO SRAMs, but in a separate I/O configuration.

Like a SigmaQuad SRAM, a SigmaSIO DDR-II SRAM can execute an alternating sequence of reads and writes. However, doing

so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would

keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read

commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts

the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice

the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device.

SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO

SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic

between two electrically independent busses is desired.

Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because

random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are

based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how

the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and

disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to

the application at hand.

Burst of 2 Sigma SIO-II SRAM DDR Read

The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on

the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is

clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data

chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K.

Burst of 2 Sigma SIO-II SRAM DDR Write

The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the

R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.