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GS8673ET18 Datasheet(PDF) 3 Page - GSI Technology |
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GS8673ET18 Datasheet(HTML) 3 Page - GSI Technology |
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3 / 34 page  GS8673ET18/36BK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 5/2012 3/34 © 2011, GSI Technology 2M x 36 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VDD VDDQ VDD VDDQ MCL MCL (CFG) MCL ZQ PZT1 VDDQ VDD VDDQ VDD B VSS DQ35 VSS NUI MVQ MCL NC (RSVD)) MCL (SIOM) PZT0 NUI VSS DQ0 VSS C DQ26 VDDQ NUI VDDQ VSS SA VDD SA VSS VDDQ NUI VDDQ DQ9 D VSS DQ34 VSS NUI SA VDDQ NC (288 Mb) VDDQ NC (144 Mb) NUI VSS DQ1 VSS E DQ25 VDDQ NUI VDD VSS SA VSS SA VSS VDD NUI VDDQ DQ10 F VSS DQ33 VSS NUI SA VDD VDDQ VDD SA NUI VSS DQ2 VSS G DQ24 DQ32 NUI NUI VSS SA MZT1 SA VSS NUI NUI DQ3 DQ11 H DQ23 VDDQ NUI VDDQ SA VDDQ R/W VDDQ SA VDDQ NUI VDDQ DQ12 J VSS DQ31 VSS NUI VSS SA VSS SA VSS NUI VSS DQ4 VSS K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0 L CQ1 VSS QVLD1 VSS KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0 M VSS DQ22 VSS NUI VSS SA VSS SA VSS NUI VSS DQ13 VSS N DQ30 VDDQ NUI VDDQ DLL VDDQ LD VDDQ MCH VDDQ NUI VDDQ DQ5 P DQ29 DQ21 NUI NUI VSS SA MZT0 SA VSS NUI NUI DQ14 DQ6 R VSS DQ20 VSS NUI MCH VDD VDDQ VDD RST NUI VSS DQ15 VSS T DQ28 VDDQ NUI VDD VSS SA VSS SA VSS VDD NUI VDDQ DQ7 U VSS DQ19 VSS NUI NUI VDDQ AZT1 VDDQ NUI NUI VSS DQ16 VSS V DQ27 VDDQ NUI VDDQ VSS NUI (x18) VDD SA (B2) VSS VDDQ NUI VDDQ DQ8 W VSS DQ18 VSS NUI TCK RLM0 NC (RSVD) MCL TMS NUI VSS DQ17 VSS Y VDD VDDQ VDD VDDQ TDO ZT RLM1 MCL TDI VDDQ VDD VDDQ VDD Notes: 1. Pins 5A, 6B, and 7A are reserved for future use. They must be tied Low. 2. Pins 5R and 9N are reserved for future use. They must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration. 4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration. 5. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low. 6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device. 7. Pin 9D is reserved as address pin SA for 144Mb devices. It is a true no-connect in this device. 8. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device. 9. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low. 10. Pins 8W and 8Y are reserved for internal use only. They must be tied Low. 11. Pins 7B and 7W are reserved for future use. They are true no-connects in this device. |
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