FlexBus

MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2

Freescale Semiconductor

9

8.1

FlexBus AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the system clock.

Table 10. FlexBus AC Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

Frequency of Operation

30

66

Mhz

1

NOTES:

1

The frequency of operation is the same as the PCI frequency of operation. The MCF547X supports a single

external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI.

FB1

Clock Period (CLKIN)

15.15

33.33

ns

2

2

Max cycle rate is determined by CLKIN and how the user has the system PLL configured.

FB2

Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0],

R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)

—7.0

ns

3

3

Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section 9.2, “DDR SDRAM AC

Timing Characteristics” for SDCS[3:0] timing.

FB3

Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0],

R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)

1—

ns

4

The FlexBus supports programming an extension of the address hold. Please consult the MCF547X

specification manual for more information.

FB4

Data Input Setup

3.5

—

ns

FB5

Data Input Hold

0

—

ns

FB6

Transfer Acknowledge (TA) Input Setup

4

—

ns

FB7

Transfer Acknowledge (TA) Input Hold

0

—

ns

FB8

Address Output Valid (PCIAD[31:0])

—

7.0

ns

5

5

These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address

signals.

FB9

Address Output Hold (PCIAD[31:0])

0

—

ns

5