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MT8888C Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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MT8888C Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
1 / 25 page 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. Features • Central office quality DTMF transmitter/receiver • Low power consumption • High speed Intel micro interface • Adjustable guard time • Automatic tone burst mode • Call progress tone detection to -30 dBm Applications • Credit card systems • Paging systems • Repeater systems/mobile radio • Interconnect dialers • Personal computers Description The MT8888C is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability. The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT8888C utilizes an Intel micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. September 2005 Ordering Information MT8888CE 20 Pin PDIP Tubes MT8888CS 20 Pin SOIC Tubes MT8888CN 24 Pin SSOP Tubes MT8888CP 28 Pin PLCC Tubes MT8888CE1 20 Pin PDIP* Tubes MT8888CS1 20 Pin SOIC* Tubes MT8888CN1 24 Pin SSOP* Tubes MT8888CP1 28 Pin PLCC* Tubes MT8888CPR 28 Pin PLCC Tape & Reel MT8888CSR 20 Pin SOIC Tape & Reel MT8888CSR1 20 Pin SOIC* Tape & Reel MT8888CPR1 28 Pin PLCC* Tape & Reel *Pb Free Matte Tin -40 °C to +85°C MT8888C Integrated DTMF Transceiver with Intel Micro Interface Data Sheet Figure 1 - Functional Block Diagram TONE IN+ IN- GS OSC1 OSC2 VDD VRef VSS ESt St/GT D0 D1 D2 D3 IRQ/CP RD CS WR RS0 ∑ D/A Converters Row and Column Counters Transmit Data Register Data Bus Buffer Tone Burst Gating Cct. + - Oscillator Circuit Bias Circuit Control Logic Digital Algorithm and Code Converter Control Logic Steering Logic Status Register Control Register A Control Register B Receive Data Register Interrupt Logic I/O Control Low Group Filter High Group Filter Dial Tone Filter |
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