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PI6C3991-5IJ Datasheet(PDF) 10 Page - Pericom Semiconductor Corporation |
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PI6C3991-5IJ Datasheet(HTML) 10 Page - Pericom Semiconductor Corporation |
10 / 11 page 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 10 PS8450B 04/09/01 PI6C3991 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer - SuperClock® Figure8.Board-to-BoardClockDistribution Figure 8 shows the PI6C3991 connected in series to construct a zero skew clock distribution tree between boards. Delays of the down stream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero- FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 System Clock REF LOAD Z0 FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD Z0 LOAD LOAD LOAD Z0 Z0 L1 L2 L3 L4 delay clock tree. Cascaded clock buffers will accumulate low-fre- quency jitter because of the non-ideal filtering characteristics of the PLLfilter.Itisrecommendedthatnotmorethantwoclockbuffersbe connected in series. |
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