S93663PBT datasheet(4/14 Pages) ETC

Part #	S93663PBT

Description	Voltage Monitor and Reset Controller

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S93662/S93663

2012 2.0 4/18/00

writing or clearing of the device. Data can be read

normally from the device regardless of the write enable/

disable status.

Erase All

Upon receiving an ERAL command, the CS (Chip

Select) pin must be deselected for a minimum of 250ns

(tCSMIN). The falling edge of CS will start the self clocking

clear cycle of all memory locations in the device. The

clocking of the SK pin is not necessary after the device

has entered the self clocking mode. The ready/busy

status of the S93662/663 can be determined by select-

ing the device and polling the DO pin. Once cleared, the

contents of all memory bits return to a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

250ns (tCSMIN). The falling edge of CS will start the self

clocking data write to all memory locations in the device.

The clocking of the SK pin is not necessary after the

device has entered the self clocking mode. The ready/

busy status of the S93662/663 can be determined by

selecting the device and polling the DO pin. It is not

necessary for all memory locations to be cleared before

the WRAL command is executed.

Page Write

93662 - Assume WEN has been issued. The host will

then take CS high, and begin clocking in the start bit,

write command and 9-bit byte address immediately

followed by the first byte of data to be written. The host

can then continue clocking in 8-bit bytes of data with

each byte to be written to the next higher address.

Internally the address pointer is incremented after

receiving each group of eight clocks; however, once

the address counter reaches x xxxx 1111 it will roll over

to x xxxx 0000 with the next clock. After the last bit is

clocked in no internal write operation will occur until CS

is brought low.

93663 - Assume WEN has been issued. The host will

then take CS high, and begin clocking in the start bit,

write command and 8-bit byte address immediately

followed by the first 16-bit word of data to be written.

The host can then continue clocking in 16-bit words of

data with each word to be written to the next higher

address. Internally the address pointer is incremented

after receiving each group of sixteen clocks; however,

once the address counter reaches xxxx x111 it will roll

over to xxxx x000 with the next clock. After the last bit

is clocked in no internal write operation will occur until

CS is brought low.

Continuous Read

This begins just like a standard read with the host

issuing a read instruction and clocking out the data

byte [word]. If the host then keeps CS high and

continues generating clocks on SK, the S93662/663

will output data from the next higher address location.

The S93662/663 will continue incrementing the ad-

dress and outputting data so long as CS stays high. If

the highest address is reached, the address counter

will roll over to address 0000. . CS going low will reset

the instruction register and any subsequent read must

be initiated in the normal manner of issuing the com-

mand and address.

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