06 | Keysight | Infiniium DCA-X 86100D Wide-Bandwidth Oscilloscope Mainframe and Modules - Data Sheet

Mainframe specifications (Continued)

Option STR (standard trigger)

Option ETR (enhanced trigger)

Trigger modes

Free run

Free run

DC to 100 MHz

DC to 100 MHz

DC to 3.2 GHz

Full bandwidth

DC to 3.2 GHz

External divided trigger

N/A

3 to 13 GHz (15 GHz, 32 GHz with Option PTB)

PatternLock

N/A

50 MHz to 13 GHz (50 MHz to 15 GHz)

N/A

Yes, supported

Jitter

Characteristic

Maximum

(2.4 to 4 GHz) 120 fs (4 to 9 GHz) 90 fs (9 to 44 GHz)

Option PTB

N/A

Trigger sensitivity

200 mV

minimum pulse width)

200 mV

Option PTB)

Trigger configuration

Trigger level adjustment

–1 to + 1 V

AC coupled

Edge select

Positive or negative

N/A

Normal or High sensitivity

N/A

Trigger gating

Gating input levels

Disable: 0 to 0.6 V, Enable: 3.5 to 5 V

(TTL compatible)

Pulse width > 500 ns, period > 1 μs

Gating delay

Disable: 27 μs + trigger period +

Maximum time displayed

Enable: 100 ns

Trigger impedance

Nominal impedance

50 Ω

Reflection

< 10% for 100 ps rise time

Connector type

3.5 mm (male)

Maximum trigger signal

2 V peak-to-peak

1. The freerun trigger mode internally generates an asynchronous trigger that allows viewing the sampled signal amplitude without an external trigger signal

but provides no timing information unless a precision timebase is used in Eye/Mask mode. Freerun is useful in troubleshooting external trigger problems.

2. The sampled input signal timing is recreated by using an externally supplied trigger signal that is synchronous with the sampled signal input.

3. The DC to 100 MHz mode is used to minimize the effect of high frequency signals or noise on a low frequency trigger signal.

4. Measured at 2.5 GHz with the triggering level adjusted for optimum trigger.

5. High Sensitivity Hysteresis mode improves the high frequency trigger sensitivity but is not recommended when using noisy, low frequency signals that may

result in false triggers without normal hysteresis enabled.

6. Slew rate ≥ 2 V/ns.

7. The Module Bay Trigger routes trigger signals from the module’s rear panel to the mainframe. 86100D-ETR is recommended when using a DCA module

equipped with a rear-panel trigger circuit. Examples include 54754A, 83496x, and 86108A/B modules. If operating these modules in an 86100D with Option

STR, an external cable (such as P/N 5062-6690) must be connected from the module’s front panel trigger/clock output to the 86100D’s trigger input.

8. In precision timebase (PTB) operation with 750 mV input (500 mV input, 9 to 44 GHz).

Specifications (Continued)