SN65HVD10,SN65HVD10Q,SN75HVD10

SN65HVD11,SN65HVD11Q,SN75HVD11

SN65HVD12,SN75HVD12

SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003

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7

PARAMETER MEASUREMENT INFORMATION

and Voltage and Current Definitions

Loading Test Circuit

60

Ω ±1%

IOA

VOD

54

Ω ±1%

0 or 3 V

VOD

0 or 3 V

VOA

VOB

IOB

DE

VCC

II

VI

A

B

_

+

−7 V < V(test) < 12 V

DE

VCC

A

B

D

375

Ω ±1%

375

Ω ±1%

VOC

27

Ω ± 1%

Input

A

B

VA

VB

VOC(PP)

∆VOC(SS)

VOC

27

Ω ± 1%

CL = 50 pF ±20%

D

A

B

DE

VCC

Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω

CL Includes Fixture and

Instrumentation Capacitance

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage

VOD

RL = 54 Ω

± 1%

50

Ω

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

tPLH

tPHL

1.5 V

1.5 V

3 V

≈ 2 V

≈ −2 V

90%

10%

0 V

VI

VOD

tr

tf

CL = 50 pF ±20%

CL Includes Fixture

and Instrumentation

Capacitance

D

A

B

DE

VCC

VI

Input

Generator

90%

0 V

10%

Figure 4. Driver Switching Test Circuit and Voltage Waveforms

RL = 110 Ω

± 1%

Input

Generator

50

Ω

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

3 V

S1

0.5 V

3 V

0 V

VOH

≈ 0 V

tPHZ

tPZH

1.5 V

1.5 V

VI

VO

CL = 50 pF ±20%

CL Includes Fixture

and Instrumentation

Capacitance

D

A

B

DE

VO

VI

2.3 V

Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms