SN65HVD10,SN65HVD10Q,SN75HVD10

SN65HVD11,SN65HVD11Q,SN75HVD11

SN65HVD12,SN75HVD12

SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003

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8

Input

Generator

50

Ω

3 V

VO

S1

3 V

1.5 V

1.5 V

tPZL

tPLZ

2.3 V

0.5 V

≈ 3 V

0 V

VOL

VI

VO

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

RL = 110 Ω

± 1%

CL = 50 pF ±20%

CL Includes Fixture

and Instrumentation

Capacitance

D

A

B

DE

VI

≈ 3 V

Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

VID

VA

VB

IO

A

B

IB

VO

R

IA

VIC

VA + VB

2

Figure 7. Receiver Voltage and Current Definitions

Input

Generator

50

Ω

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

VO

1.5 V

0 V

1.5 V

1.5 V

3 V

VOH

VOL

1.5 V

10%

1.5 V

tPLH

tPHL

tr

tf

90%

VI

VO

CL = 15 pF ±20%

CL Includes Fixture

and Instrumentation

Capacitance

A

B

RE

VI

R

0 V

90%

10%

Figure 8. Receiver Switching Test Circuit and Voltage Waveforms