TMP100, 101

8

SBOS231C

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BUS OVERVIEW

The device that initiates the transfer is called a “master,” and

the devices controlled by the master are “slaves.” The bus

must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates

the START and STOP conditions.

To address a specific device, a START condition is initiated,

indicated by pulling the data-line (SDA) from a HIGH to LOW

logic level while SCL is HIGH. All slaves on the bus shift in the

slave address byte, with the last bit indicating whether a read

or write operation is intended. During the ninth clock pulse,

the slave being addressed responds to the master by gener-

ating an Acknowledge and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock pulses

followed by an Acknowledge Bit. During data transfer SDA

must remain stable while SCL is HIGH, as any change in SDA

while SCL is HIGH will be interpreted as a control signal.

Once all data has been transferred, the master generates a

STOP condition indicated by pulling SDA from LOW to HIGH,

while SCL is HIGH.

WRITING/READING TO THE TMP100 AND TMP101

Accessing a particular register on the TMP100 and TMP101

is accomplished by writing the appropriate value to the

Pointer Register. The value for the Pointer Register is the

TMP101 requires a value for the Pointer Register. (Refer to

Figure 6.)

When reading from the TMP100 and TMP101, the last value

stored in the Pointer Register by a write operation is used to

determine which register is read by a read operation. To

change the register pointer for a read operation, a new value

must be written to the Pointer Register. This is accomplished

followed by the Pointer Register Byte. No additional data is

required. The master can then generate a START condition

to initiatnlthe read command. See Figure 7 for details of this

sequence. If repeated reads from the same register are

desired, it is not necessary to continually send the Pointer

Register bytes as the TMP100 and TMP101 will remember

the Pointer Register value until it is changed by the next write

operation.

SLAVE MODE OPERATIONS

The TMP100 and TMP101 can operate as slave receivers or

slave transmitters.

Slave Receiver Mode:

The first byte transmitted by the master is the slave address, with

reception of a valid address. The next byte transmitted by the

master is the Pointer Register. The TMP100 or TMP101 then

acknowledges reception of the Pointer Register byte. The next

byte or bytes are written to the register addressed by the Pointer

register. The TMP100 and TMP101 will acknowledge recep-

tion of each data byte. The master may terminate data

transfer by generating a START or STOP condition.

Slave Transmitter Mode:

The first byte is transmitted by the master and is the slave

reception of a valid slave address. The next byte is transmit-

ted by the slave and is the most significant byte of the

register indicated by the Pointer Register. The master ac-

knowledges reception of the data byte. The next byte trans-

mitted by the slave is the least significant byte. The master

acknowledges reception of the data byte. The master may

terminate data transfer by generating a Not-Acknowledge on

reception of any data byte, or generating a START or STOP

condition.

SMBus ALERT FUNCTION

The TMP101 supports the SMBus Alert function. When the

TMP101 is operating in Interrupt Mode (TM = 1), the ALERT

pin of the TMP101 may be connected as an SMBus Alert

signal. When a master senses that an ALERT condition is

present on the ALERT line, the master sends an SMBus Alert

command (00011001) on the bus. If the ALERT pin of the

TMP101 is active, the TMP101 will acknowledge the SMBus

Alert command and respond by returning its slave address

on the SDA line. The eighth bit (LSB) of the slave address

Refer to Figure 8 for details of this sequence.

If multiple devices on the bus respond to the SMBus Alert

command, arbitration during the slave address portion of the

SMBus alert command will determine which device will clear

its ALERT status. If the TMP101 wins the arbitration, its

ALERT pin will become inactive at the completion of the

SMBus Alert command. If the TMP101 loses the arbitration,

its ALERT pin will remain active.

The TMP100 will also respond to the SMBus ALERT com-

mand if its TM bit is set to 1. Since it does not have an ALERT

pin, the master needs to periodically poll the device by

issuing an SMBus Alert command. If the TMP100 has gen-

erated an ALERT, it will acknowledge the SMBus Alert

command and return its slave address in the next byte.

GENERAL CALL

address (0000000) if the eighth bit is 0. The device will

acknowledge the General Call address and respond to com-

mands in the second byte. If the second byte is 00000100,

the TMP100 and TMP101 will latch the status of their

address pins, but will not reset. If the second byte is 00000110,

the TMP100 and TMP101 will latch the status of their

address pins and reset their internal registers.