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AMIS-30622 Datasheet(PDF) 8 Page - ON Semiconductor |
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AMIS-30622 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 50 page AMIS−30622 http://onsemi.com 8 AC PARAMETERS The AC parameters are guaranteed for temperature and VBB in the operating range unless otherwise specified. Table 6. AC PARAMETERS Symbol Pin(s) Parameter Test Conditions Min Typ Max Unit POWERUP Tpu Power−up time Guaranteed by design 10 ms INTERNAL OSCILLATOR fosc Frequency of internal oscillator VBB = 14 V 3.6 4.0 4.4 MHz I2C TRANSCEIVER (STANDARD MODE) fSCL SDA SCK SCL clock frequency 100 kHz tHD,START Hold time (repeated) START condition. After this period the first clock pulse is generated. 4.0 ms tLOW LOW period of the SCK clock 4.7 ms tHIGH HIGH period of the SCK clock 4.0 ms tSU,START Set−up time for a repeated START condition 4.7 ms tHD,DATA Data hold time for I2C bus devices 0 (Note 16) 3.45 (Note 17) ms tSU,DATA Data set−up time 250 ns tR Rise time of SDA and SCK signals 1.0 ms tF Fall time of SDA and SCK signals 0.3 ms tSU,STOP Set−up time for STOP condition 4.0 ms tBUF Bus free time between STOP and START condition 4.7 ms I2C TRANSCEIVER (FAST MODE) fSCL SDA SCK SCL clock frequency 360 kHz tHD,START Hold time (repeated) START condition. After this period the first clock pulse is generated. 0.6 ms tLOW LOW period of the SCK clock 1.3 ms tHIGH HIGH period of the SCK clock 0.6 ms tSU,START Set−up time for a repeated START condition 0.6 ms tHD,DATA Data hold time for I2C bus devices 0 (Note 16) 0.9 (Note 17) ms tSU,DATA Data set−up time 100 (Note 18) ns tR Rise time of SDA and SCK signals 20 + 0.1 CB 300 ns tF Fall time of SDA and SCK signals 20 + 0.1 CB 300 ns tSU,STOP Set−up time for STOP condition 0.6 ms tBUF Bus free time between STOP and START condition 1.3 ms 15.The maximum number of connected I2C devices is dependent on the number of available addresses and the maximum bus capacitance to still guarantee the rise and fall times of the bus signals. 16.An I2C device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 17.The maximum tHD,DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 18.A Fast−mode I2C−bus device can be used in a standard−mode I2C bus system, but the requirement tSU,DATA w 250 ns must than be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU,DATA = 1000 + 250 = 1250 ns (according to the standard−mode I2C−bus specification) before the SCL line is released. |
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