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NCL30100SNT1G Datasheet(PDF) 7 Page - ON Semiconductor |
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NCL30100SNT1G Datasheet(HTML) 7 Page - ON Semiconductor |
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7 / 27 page  NCL30100 http://onsemi.com 7 APPLICATION INFORMATION The NCL30100 implements a peak current mode control scheme with a quasi−fixed OFF time. An optional input feedforward voltage control is provided to enhance regulation response with widely varying input voltages. Only a few external components are necessary to implement the buck converter. The NCL30100 incorporates the following features: • Very Low Startup Current: The patented internal supply block is specially designed to offer a very low current consumption during startup. • Negative Current Sensing: By sensing the total current, this technique does not impact the MOSFET driving voltage (VGS) during switching. Furthermore, the programming resistor together with the pin capacitance forms a residual noise filter which blanks spurious spikes. This approach also supports a flexible resistor selection. Finally unlike a positive sensing approach, there is virtually no power dissipation in the current sense resistor thus improving efficiency. • Controller architecture supports high brightness LED drive current requirements: Selection of the external n−channel MOSFET can be easily optimized based on operation voltage, drive current and size giving the designer flexibility to easily make design tradeoffs. • Typical $5.5% Current Regulation: The ICS pin offers $5.5% from 0 to 85°C (+5.5% −9.5% across −40°C to 125 °C) accuracy of the current typically, so the LED peak current is precisely controlled • No output capacitor is needed: By operating the controller in continuous conduction mode, it is possible to eliminate the bulky output filter capacitor. The following section describes in detail each of the control blocks Current Sensing Block The NCL30100 utilizes a technique called negative current sensing which is used to set the peak current through the switch and the inductor. This approach offers several benefits over traditional positive current sensing. • Maximum peak voltage across the current sense resistor is user controlled and can be optimized by changing the value of the shift resistor. • The gate drive capability is improved because the current sense resistor is located out of the gate driver loop and does not deteriorate the switch on and also switch off gate drive amplitude. • Natural leading edge blanking is filter switching noise at FET turn−in • The CS pin is not exposed to negative voltage, which could induce a parasitic substrate current within the IC and distort the surrounding internal circuitry. The current sensing circuit is shown in Figure 15. Figure 15. Primary Current Sensing Input Voltage Regulator RCS Rshift Iprimary GND CS IVC 12.5−50 mA To Latch VCS Vshift |
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