NCP81071

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2

VDD

VDD

VDD

VDD

Ref

Ref

Ref

Ref

Logic

A Channel

Logic

B Channel

UVLO

VDD

VDD

VDD

VDD

INA

ENA

GND

INB

ENB

OUTA

OUTB

VDD

Figure 1. NCP81071 Block Diagram

NCP81071A

NCP81071B

NCP81071C

VDD

VDD

Ref

Ref

Ref

Ref

Logic

A Channel

Logic

B Channel

UVLO

VDD

VDD

VDD

VDD

INA

ENA

GND

INB

ENB

OUTA

OUTB

VDD

VDD

VDD

VDD

Ref

Ref

Ref

Ref

Logic

A Channel

Logic

B Channel

UVLO

VDD

VDD

VDD

VDD

INA

ENA

GND

INB

ENB

OUTA

OUTB

VDD

Table 1. PIN DESCRIPTION

Pin No.

Symbol

Description

1

ENA

Enable input for the driver channel A with logic compatible threshold and hysteresis. This pin is used to en-

able and disable the driver output. It is internally pulled up to VDD with a 200 k

W resistor for active high op-

eration. The output of the pin when the device is disabled will be always low.

2

INA

Input of driver channel A which has logic compatible threshold and hysteresis. If not used, this pin should be

connected to either VDD or GND. It should not be left unconnected.

3

GND

Common ground. This ground should be connected very closely to the source of the power MOSFET.

4

INB

Input of driver channel B which has logic compatible threshold and hysteresis. If not used, this pin should be

connected to either VDD or GND. It should not be left unconnected.

5

OUTB

Output of driver channel B. The driver is able to provide 5 A drive current to the gate of the power MOSFET.

6

VDD

Supply voltage. Use this pin to connect the input power for the driver device.

7

OUTA

Output of driver channel A. The driver is able to provide 5 A drive current to the gate of the power MOSFET.

8

ENB

Enable input for the driver channel B with logic compatible threshold and hysteresis. This pin is used to en-

able and disable the driver output. It is internally pulled up to VDD with a 200 k

W resistor for active high op-

eration. The output of the pin when the device is disabled will be always low.