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NCP81155 Datasheet(PDF) 7 Page - ON Semiconductor |
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NCP81155 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 8 page NCP81155 www.onsemi.com 7 APPLICATIONS INFORMATION The NCP81155 gate driver is a MOSFET driver designed for driving two N−channel MOSFETs in a synchronous buck or buck−boost topology. Low−Side Driver The low−side driver is designed to drive a ground referenced low RDS(on) N−channel MOSFET. The voltage supply for the low−side driver is internally connected to the VCC and GND pins. High−Side Driver The high−side driver is designed to drive a floating low RDS(on) N−channel MOSFET. The gate voltage for the high−side driver is developed by a bootstrap circuit referenced to the SW pin. The bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. When the NCP81155 is starting up, the SW pin is held at ground, allowing the bootstrap capacitor to charge up to VCC through the bootstrap diode. When the PWM input is driven high, the high−side driver will turn on the high−side MOSFET using the stored charge of the bootstrap capacitor. As the high−side MOSFET turns on, the SW pin rises. When the high−side MOSFET is fully turned on, SW will settle to VIN and BST will settle to VIN + VCC (excluding parasitic ringing). Bootstrap Circuit The bootstrap circuit relies on an external charge storage capacitor (CBST) and an integrated diode to provide current to the high−side driver. A multi−layer ceramic capacitor (MLCC) with a value greater than 100 nF should be used for CBST. Power Supply Decoupling The NCP81155 can source and sink relatively large currents to the gate pins of the MOSFETs. In order to maintain a constant and stable supply voltage, a low−ESR capacitor should be placed near the VCC and GND pins. A MLCC between 1 mF and 4.7 mF is typically used. Undervoltage Lockout DRVH and DRVL are low until VCC reaches the VCC UVLO threshold, typically 4.35 V. Once VCC reaches this threshold, the PWM signal will control DRVH and DRVL. There is a 200 mV hysteresis on VCC UVLO. There are pull−down resistors on DRVH and DRVL to prevent the gates of the MOSFETs from accumulating enough charge to turn on when the driver is powered off. Bi−Directional EN Signal The Enable pin (EN) is used to disable the DRVH and DRVL outputs to prevent power transfer. When EN is above the ENHI threshold, DRVH and DRVL change their states according to the PWM input. A UVLO fault turns on the internal MOSFET that pulls the EN pin towards ground. By connecting EN to the DRON pin of a controller, the controller is alerted when the driver encounters a fault condition. PWM Input Switching PWM between logic−high and logic−low states will allow the driver to operate in continuous conduction mode as long as VCC is greater than the UVLO threshold and EN is high. The threshold limits are specified in the electrical characteristics table in this datasheet. Refer to Figure 2 for the gate timing diagrams. When PWM is set above PWMHI, DRVL will first turn off after a propagation delay of tpdlDRVL. To ensure non−overlap between DRVL and DRVH, there is a delay of tpdhDRVH from the time DRVL falls to 1 V, before DRVH is allowed to turn on. When PWM falls below PWMLO, DRVH will first turn off after a propagation delay of tpdlDRVH. To ensure non−overlap between DRVH and DRVL, there is a delay of tpdhDRVL from the time DRVH – SW falls to 1 V, before DRVL is allowed to turn on. Thermal Considerations As power in the NCP81155 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCP81155 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCP81155 can handle is given by: P D(MAX) + [T J(MAX) * TA] RqJA (eq. 1) Since TJ is not recommended to exceed 150 °C, the NCP81155, soldered on to a 645 mm2 copper area, using 1 oz. copper and FR4, can dissipate up to 2.3 W when the ambient temperature (TA) is 25 °C. The power dissipated by the NCP81155 can be calculated from the following equation: P D [ VCC [ n HS Qg HS ) nLS Qg LS f ) I standby] (eq. 2) Where nHS and nLS are the number of high−side and low−side FETs, respectively, QgHS and QgLS are the gate charges of the high−side and low−side FETs, respectively and f is the switching frequency of the converter. |
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