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DA14581 Datasheet(PDF) 5 Page - Dialog Semiconductor |
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DA14581 Datasheet(HTML) 5 Page - Dialog Semiconductor |
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5 / 152 page  Datasheet Revision 3.0 18-Dec-2015 CFR0011-120-00-FM Rev 5 5 of 152 © 2015 Dialog Semiconductor DA14581 Low Power Bluetooth Smart SoC with optimized boot time FINAL Table 1: Pin description PIN NAME TYPE Drive (mA) Reset state (Note ) DESCRIPTION General Purpose I/Os P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. P1_0 P1_1 P1_2 P1_3 P1_4/SWCLK P1_5/SW_DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PU INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. This signal is the JTAG clock by default This signal is the JTAG data I/O by default P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P2_8 P2_9 DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. NOTE: This port is only available on the QFN40 package. P3_0 to P3_7 DIO 4.8 I-PD Not supported. Debug interface SWDIO/P1_5 DIO 4.8 I-PU INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Can also be used as a GPIO SW_CLK/ P1_4 DIO 4.8 I-PD INPUT JTAG clock signal. Can also be used as a GPIO Clocks XTAL16Mp AI INPUT. Crystal input for the 16 MHz XTAL XTAL16Mm AO OUTPUT. Crystal output for the 16 MHz XTAL XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL Quadrature decoder QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports SPI bus interface SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports SPI_DI DI INPUT. SPI Data input. Mapped on Px ports |
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