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DA7218-00U32 Datasheet(PDF) 5 Page - Dialog Semiconductor |
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DA7218-00U32 Datasheet(HTML) 5 Page - Dialog Semiconductor |
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5 / 173 page  DA7218 Ultra-Low Power Stereo Codec Datasheet Revision 2.5 01 Sep 2016 CFR0011-120-00 5 of 173 © 2016 Dialog Semiconductor 9.4.1 Digital to Analog Converter.................................................................................. 54 9.4.2 Headphone Amplifiers ......................................................................................... 54 9.4.3 Headphone Detection .......................................................................................... 57 9.4.4 Jack Detection ..................................................................................................... 57 9.4.4.1 Automatic MICBIAS1 Control .......................................................... 57 9.4.5 Mono, Stereo and Load Detection ....................................................................... 57 9.4.6 Charge Pump Control .......................................................................................... 58 9.4.6.1 Charge Pump Initial and Switching Current .................................... 59 9.4.7 Tracking the Demands on the Charge Pump Output .......................................... 59 9.4.7.1 cp_mchange = 00 (Manual Mode)................................................... 59 9.4.7.2 cp_mchange = 01 (Tracking the PGA Gain Setting) ....................... 59 9.4.7.3 cp_mchange = 10 (Tracking the DAC Signal Setting)..................... 59 9.4.7.4 cp_mchange = 11 (Tracking the Output Signal Magnitude) ............ 60 9.4.8 Specifying Clock Frequencies when Tracking the Charge Pump Output Demand ............................................................................................................... 61 9.4.9 Other Charge Pump Controls .............................................................................. 61 9.4.10 True-Ground Supply Mode .................................................................................. 61 9.5 Phase Locked Loop ............................................................................................................ 61 9.5.1 PLL Bypass Mode................................................................................................ 61 9.5.2 Normal PLL Mode (DAI Master) .......................................................................... 62 9.5.3 Example Calculation of the Feedback Divider Setting: ....................................... 63 9.5.4 Sample Rate Matching PLL Mode (DAI Slave) ................................................... 63 9.5.5 MCLK Input .......................................................................................................... 64 9.5.5.1 MCLK Detection............................................................................... 64 9.5.6 Audio Reference Oscillator .................................................................................. 64 9.5.6.1 Oscillator Calibration........................................................................ 64 9.5.6.2 Procedure for Calibrating the Reference Oscillator ......................... 65 9.5.7 Internal System Clock.......................................................................................... 65 9.6 Reference Generation......................................................................................................... 65 9.6.1 Voltage References ............................................................................................. 65 9.6.2 Bias Currents ....................................................................................................... 65 9.6.3 Voltage Levels ..................................................................................................... 65 9.6.3.1 Digital Regulator .............................................................................. 65 9.6.3.2 Digital Input/Output Pins Voltage Level ........................................... 66 9.7 I 2C Control Interface............................................................................................................ 66 9.8 Digital Audio Interface ......................................................................................................... 69 9.8.1 DAI Channels....................................................................................................... 70 9.8.2 DAI WCLK Tristate Mode .................................................................................... 71 9.9 Interrupt Control .................................................................................................................. 71 9.9.1 Level Detect Events............................................................................................. 71 9.9.2 Jack Detect Events .............................................................................................. 71 9.10 System Settings .................................................................................................................. 72 9.10.1 Sample Rate ........................................................................................................ 72 9.10.2 Gain Ramp Rate .................................................................................................. 72 9.10.3 Program Counter Control..................................................................................... 72 9.10.4 Soft Reset ............................................................................................................ 72 10 Register Maps and Definitions................................................................................................... 73 |
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Similar Description - DA7218-00U32 |
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