3959

DMOS FULL-BRIDGE

PWM MOTOR DRIVER

www.allegromicro.com

5

FUNCTIONAL DESCRIPTION

be decoupled with a 0.22

µF capacitor to ground. V

internally monitored and in the case of a fault condition,

the outputs of the device are disabled.

Charge Pump. The charge pump is used to generate a

side DMOS gates. A 0.22

µF ceramic capacitor should be

connected between CP1 and CP2 for pumping purposes.

A 0.22

µF ceramic capacitor should be connected between

DMOS devices. The CP voltage is internally monitored

and, in the case of a fault condition, the source outputs of

the device are disabled.

PHASE Logic. The PHASE input terminal determines if

the device is operating in the “forward” or “reverse” state.

PHASE

0

Low

High

1

High

Low

ENABLE Logic. The ENABLE input terminal allows

external PWM. ENABLE high turns on the selected sink-

source pair. ENABLE low switches off the source driver

or the source and sink driver, depending on EXT MODE,

and the load current decays. If ENABLE is kept high, the

current will rise until it reaches the level set by the internal

current-control circuit.

ENABLE

Outputs

0

Chopped

1On

EXT MODE Logic. When using external PWM current

control, the EXT MODE input determines the current path

during the chopped cycle. With EXT MODE low, fast

decay mode, the opposite pair of selected outputs will be

enabled during the off cycle. With EXT MODE high,

slow decay mode, both sink drivers are on with ENABLE

low.

EXT MODE

Decay

0

Fast

1

Slow

Current Regulation. Load current is regulated by an

internal fixed off-time PWM control circuit. When the

outputs of the DMOS H bridge are turned on, the current

increases in the motor winding until it reaches a trip value

At the trip point, the sense comparator resets the source-

enable latch, turning off the source driver. The load

inductance then causes the current to recirculate for the

fixed off-time period. The current path during

recirculation is determined by the configuration of slow/

mixed/fast current-decay mode via PFD1 and PFD2.

Oscillator. The PWM timer is based on an internal

51 k

Ω resistor. The allowable range of the resistor is from

20 k

Ω to 100 kΩ.

ground.

Fixed Off Time. The A3959 is set for a fixed off time of

96 cycles of the internal oscillator, typically 24

µs with a

4 MHz oscillator.