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CAT809SSDI-GT3 Datasheet(PDF) 6 Page - ON Semiconductor |
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CAT809SSDI-GT3 Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 11 page CAT803, CAT809, CAT810 http://onsemi.com 6 Detailed Descriptions Reset Timing The reset signal is asserted LOW for the CAT803/CAT809 and HIGH for the CAT810 when the power supply voltage falls below the threshold trip voltage and remains asserted for at least 140 ms after the power supply voltage has risen above the threshold. 0 V CAT803, CAT809 5 V 0 V 5 V RESET (140 ms minimum) Reset Timeout Period CAT810 0 V 5 V Figure 6. Reset Timing Diagram TR TD VTH VCC RESET VCC Transient Response The CAT803/CAT809/CAT810 protect mPs against brownout failure. Short duration transients of 4 msec or less and 100 mV amplitude typically do not cause a false RESET. Figure 7 shows the maximum pulse duration of negative− going VCC transients that do not cause a reset condition. As the amplitude of the transient goes further below the threshold (increasing VTH − VCC), the maximum pulse duration decreases. In this test, the VCC starts from an initial voltage of 0.5 V above the threshold and drops below it by the amplitude of the overdrive voltage (VTH − VCC). Figure 7. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdrive RESET OVERDRIVE VTH − VCC (mV) 1000 100 10 1 0 5 10 15 20 25 30 CAT809M CAT809Z TAMB = 25°C |
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Similar Description - CAT809SSDI-GT3 |
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