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ADV7181BCP Datasheet(PDF) 11 Page - Analog Devices |
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ADV7181BCP Datasheet(HTML) 11 Page - Analog Devices |
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11 / 96 page  ADV7181B Rev. 0 | Page 11 of 96 Pin No. Mnemonic Type Function 21 XTAL1 O This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181B. In crystal mode, the crystal must be a fundamental crystal. 29 PWRDN I A logic low on this pin places the ADV7181B in a power-down mode. Refer to the I2C Register Maps section for more options on power-down modes for the ADV7181B. 30 ELPF I The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 44. 9 SFL O Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. 41 REFOUT O Internal Voltage Reference Output. Refer to Figure 44 for a recommended capacitor network for this pin. 42 CML O The CML pin is a common-mode level for the internal ADCs. Refer to Figure 44 for a recommended capacitor network for this pin. 38, 39 CAPY1, CAPY2 I ADC’s Capacitor Network. Refer to Figure 44 for a recommended capacitor network for this pin. 44 CAPC2 I ADC’s Capacitor Network. Refer to Figure 44 for a recommended capacitor network for this pin. |
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