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ADV7181B Datasheet(PDF) 7 Page - Analog Devices |
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ADV7181B Datasheet(HTML) 7 Page - Analog Devices |
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7 / 96 page  ADV7181B Rev. 0 | Page 7 of 96 TIMING SPECIFICATIONS Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Table 3. Parameter Symbol Test Conditions Min Typ Max Unit SYSTEM CLOCK AND CRYSTAL Nominal Frequency 27.00 MHz Frequency Stability ±50 ppm I2C PORT SCLK Frequency 400 kHz SCLK Min Pulse Width High t1 0.6 µs SCLK Min Pulse Width Low t2 1.3 µs Hold Time (Start Condition) t3 0.6 µs Setup Time (Start Condition) t4 0.6 µs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 µs RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio t9:t10 45:55 55:45 % Duty Cycle DATA AND CONTROL OUTPUTS Data Output Transitional Time t11 Negative Clock Edge to start of valid data. (tACCESS = t10 – t11) 3.4 ns Data Output Transitional Time t12 End of valid data to negative clock edge. (tHOLD = t9 + t12) 2.4 ns ANALOG SPECIFICATIONS Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Table 4. Parameter Symbol Test Conditions Min Typ Max Unit CLAMP CIRCUITRY External Clamp Capacitor 0.1 µF Input Impedance Clamps switched off 10 MΩ Large Clamp Source Current 0.75 mA Large Clamp Sink Current 0.75 mA Fine Clamp Source Current 60 µA Fine Clamp Sink Current 60 µA |
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Similar Description - ADV7181B |
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