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NCP367OPMUECTBG Datasheet(PDF) 10 Page - ON Semiconductor |
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NCP367OPMUECTBG Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 13 page NCP367 www.onsemi.com 10 to this option, both fast charge or USB charge are authorized with the same device. Figure 12. IOCP versus RLIM, GS = low and high, 1.5 A version 0 500 1000 1500 0 100 200 300 400 500 600 700 800 Rilim(k W) GS = High GS = Low 0 1 2 3 0 100 200 300 400 500 600 700 800 GS = Low GS = High Figure 13. Over Current Threshold versus RLIMIT 2.85 A Version Rilim (k W) Typical RLIM calculation is following: NCP367DxMUxxTBG RLIM (k W) = 249 / IOCP − 165 NCP367OxMUxxTBG RLIM (k W) = 532 / IOCP − 180 During overcurrent event, charge area is opened and FLAG output is tied to low, allowing the mController to take into account the fault event and then open the charge path. At power up (accessory is plugged on input pins), the current is limited up to ILIM during 1.8 ms (typical), to allow capacitor charge and limit inrush current. If the ILIM threshold is exceeded over 1.8 ms, the device enter in OCP burst mode until the overcurrent event disappears. VBAT Sense The connection of the VBAT pin to the positive connection of the Li ion battery pack allows preventing overvoltage transient, greater than 4.35 V. In case of wrong charger conditions, the PMOS is then opened, eliminating Battery pack over voltage which could create safety issues and temperature increasing. The 4.35 V comparator has a 150 mV built−in hysteresis. More of that, deglitch function of 2 ms is integrated to prevent voltage transients on the Battery voltage. If the battery over voltage condition exceeds deglitch time, the charge path is opened and FLAG pin is tied to low level until the VBAT is greater than 4.35 V – hysteresis. At wall adapter insertion, and if the battery is fully charged, Vbat comparator stays locked until battery needs to be recharged (4.2 V typ − 4.1 V min). A serial resistor has to be placed in series with Vbat pin and battery connection, with a 200 k W recommended value. PCB Recommendations The NCP367 integrates low RDS(on) PMOS FET, nevertheless PCB layout rules must be respected to properly evacuate the heat out of the silicon. The DFN PAD1 corresponds to the PMOS drain so must be connected to OUT plane to increase the heat transfer. Of course, in any case, this pad shall be not connected to any other potential. Following figure shows package thermal resistance of a DFN 2.2x2 mm. |
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