NIS5132 Series

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9

Undervoltage Lockout

The undervoltage lockout circuit uses a comparator with

hysteresis to monitor the input voltage. If the input voltage

drops below the specified level, the output switch will be

switched to a high impedance state.

dv/dt Circuit

The dv/dt circuit brings the output voltage up under a

linear, controlled rate regardless of the load impedance

characteristics. An internal ramp generator creates a linear

ramp, and a control circuit forces the output voltage to

follow that ramp, scaled by a factor.

The default ramp time is approximately 2 ms. This can be

modified by adding an external capacitor at the dv/dt pin.

This pin includes an internal current source of

approximately 85 nA. Since the current level is very low, it

is important to use a ceramic cap or other low leakage

capacitor. Aluminum electrolytic capacitors are not

recommended for this circuit.

The ramp time from 0 to the nominal output voltage can

be determined by the following equation, where t is in

seconds:

24e6

* 50 pF

Where:

C is in Farads

t is in seconds

Any time that the unit shuts down due to a fault, enable

shut−down, or recycling of input power, the timing capacitor

will be discharged and the output voltage will ramp from 0

at turn on.

Enable/Fault

The Enable/Fault pin is a multi−function, bidirectional pin

that can control the output of the chip as well as send

information to other devices regarding the state of the chip.

When this pin is low, the output of the fuse will be turned off.

When this pin is high the output of the fuse will be

turned−on. If a thermal fault occurs, this pin will be pulled

low to an intermediate level by an internal circuit.

To use as a simple enable pin, an open drain or open

collector device should be connected to this pin. Due to its

tri−state operation, it should not be connected to any type of

logic with an internal pullup device.

If the chip shuts down due to the die temperature reaching

its thermal limit, this pin will be pulled down to an

intermediate level. This signal can be monitored by an

external circuit to communicate that a thermal shutdown has

occurred. If this pin is tied to another device in this family

(NIS5132 or NIS5135), a thermal shutdown of one device

will cause both devices to disable their outputs. Both devices

will turn on once the fault is removed for the auto−retry

devices.

For the latching thermal device, the outputs will be

enabled after the enable pin has been pulled to ground with

an external switch and then allowed to go high or after the

input power has been recycled. For the auto retry devices,

both devices will restart as soon as the die temperature of the

device in shutdown has been reduced to the lower thermal

limit. The thermal options are listed in the ordering table.

Thermal Protection

The NIS5132 includes an internal temperature sensing

circuit that senses the temperature on the die of the power

FET. If the temperature reaches 175

°C, the device will shut

down, and remove power from the load. Output power can

be restored by either recycling the input power or toggling

the enable pin. Power will automatically be reapplied to the

load for auto−retry devices once the die temperature has

been reduced by 45

°C.

The thermal limit has been set high intentionally, to

increase the trip time during high power transient events. It

is not recommended to operate this device above 150

°C for

extended periods of time.

Figure 19. Fault/Enable Signal Levels