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TPS650860A0RSKR Datasheet(PDF) 5 Page - Texas Instruments |
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TPS650860A0RSKR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 94 page  TPS650860 www.ti.com SWCS128A – MARCH 2015 – REVISED DECEMBER 2015 Pin Functions NO. NAME I/O DESCRIPTION SMPS REGULATORS Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output 1 FBGND2 I capacitor. Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output 2 FBVOUT2 I capacitor. 3 DRVH2 O High-side gate driver output for BUCK2 controller. 4 SW2 I Switch node connection for BUCK2 controller. Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and 5 BOOT2 I SW2 pin. 6 PGNDSNS2 I Power GND connection for BUCK2. Connect to ground terminal of external low-side FET. 7 DRVL2 O Low-side gate driver output for BUCK2 controller. 5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (TYP) ceramic 8 DRV5V_2_A1 I capacitor. Shorted on board to LDO5P0 pin typically. 10 LX3 O Switch node connection for BUCK3 converter. 11 PVIN3 I Power input to BUCK3 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor. 12 FB3 I Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor. 20 LX5 O Switch node connection for BUCK5 converter. 21 PVIN5 I Power input to BUCK5 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor. 22 FB5 I Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor. 23 FB4 I Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor. 24 PVIN4 I Power input to BUCK4 converter. Bypass to ground with a 10-µF (TYP) ceramic capacitor. 25 LX4 O Switch node connection for BUCK4 converter. 29 FBVOUT1 I Remote feedback sense for BUCK1 controller. Connect to positive terminal of output capacitor. Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current 30 ILIM1 I limit of external low-side FET. 33 DRVH1 O High-side gate driver output for BUCK1 controller. 34 SW1 I Switch node connection for BUCK1 controller. Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and 35 BOOT1 I SW1 pin. 36 PGNDSNS1 I Power GND connection for BUCK1. Connect to ground terminal of external low-side FET. 37 DRVL1 O Low-side gate driver output for BUCK1 controller. 5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (TYP) ceramic 38 DRV5V_1_6 I capacitor. Shorted on board to LDO5P0 pin typically. 39 DRVL6 O Low-side gate driver output for BUCK6 controller. 40 PGNDSNS6 I Power GND connection for BUCK6. Connect to ground terminal of external low-side FET. Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and 41 BOOT6 I SW6 pin. 42 SW6 I Switch node connection for BUCK6 controller. Copyright © 2015, Texas Instruments Incorporated Pin Configuration and Functions 5 Submit Documentation Feedback Product Folder Links: TPS650860 |
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