CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 4 of 40
Pin Definitions
Signal Name
Description
I/O
Function
A0–35
Port A Data
I/O 36-bit bidirectional data port for side A.
AEA
Port A Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the
number of words in FIFO2 is less than or equal to the value in the Almost Empty A offset
register, X2 (see note 61).
AEB
Port B Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the
number of words in FIFO1 is less than or equal to the value in the Almost Empty B offset
register, X1 (see note 61).
AFA
Port A Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1 (see note 61).
AFC
Port C Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKC. It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full C offset
register, Y2 (see note 61).
B0–17
Port B Data
O
18-bit output data port for port B.
BE/FWFT
BigEndian/
First-Word Fall-
Through Select
I
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is transferred to Port B first for A-to-B data flow. For data flowing from port C to
Port A, the first word/byte written to Port C will come out as the most significant word/byte
on Port A. A LOW on BE will select Little Endian operation. In this case, the least
significant byte or word on Port A is transferred to Port B first for A-to-B data flow. For
data flowing from port C to Port A, the first word/byte written to Port C will come out as
the least significant word/byte on port A. After Master Reset, this pin selects the timing
mode. A HIGH on FWFT selects CY Standard mode, a LOW selects First-Word Fall-
Through Mode. Once the timing mode has been selected, the level on FWFT must be
static throughout device operation.
C0–17
Port CData
I
18-bit input data port for port C.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and
can be asynchronous or coincident to CLKB or CLKC. FFA/IRA, EFA/ORA, AFA, and
AEA are all synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and
can be asynchronous or coincident to CLKA or CLKC. EFB/ORB and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CLKC
Port C Clock
I
CLKC is a continuous clock that synchronizes all data transfers through Port C
and can be asynchronous or coincident to CLKA or CLKB. FFC/IRC and AFC are all
synchronized to the LOW-to-HIGH transition of CLKC.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to Read or Write
on Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to Read from Port
B. The B0–17 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
Port A Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard mode, the EFA function is selected.
EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A0–35 outputs,
available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ORB
Port B Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard mode, the EFB function is selected.
EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B0–17 outputs,
available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to Read or Write
data on Port A.
RENB
Port B Read
Enable
I
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read data
from Port B.
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