STK541UC60C-E

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8

Input / Output Timing Chart

Fig.7

Notes

*1 : Diagram shows the prevention of shoot-through via control logic. More deadtime to account for switching delay needs to be added

externally.

*2 : If lower VDD drops all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the operation will resume

immediately.

*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs

return to normal operation immediately after the upper side gat voltage rises.

*4 : In case of over current detection all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 6 to 12ms

after the over current condition is removed.

ON

OFF

HIN1,2,3

LIN1,2,3

N terminal

(BUS line)

Current

Upper

U, V, W

Lower

U ,V, W

VB1,2,3

*1

*1

OFF

ON

*2

*3

VBS undervoltage protection reset signal

VDD undervoltage protection reset voltage

-------------------------------------------------------ISD operation current level-------------------------------------------------------

Automatically reset after protection

(typ.9ms)

*4

VDD

VBS undervoltage protection reset voltage

FAULT terminal

Voltage

(at pulled-up)