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CY7C1380BV25
CY7C1382BV25
PRELIMINARY
9
Cycle Descriptions[1, 2, 3, 4]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
L
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
L
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
L
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
L
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
L
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
L
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
L
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
L
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
L
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
L
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
L
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
H
X
X
X
X
X
X
X
Hi-Z
X
Note:
1.
X = “Don't Care,” 1 = HIGH, 0 = LOW.
2.
Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3.
The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4.
CE1, CE2 and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
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