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TPS70702PWPR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS70702PWPR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 40 page www.ti.com DEVICE INFORMATION UVLO1 Comp + - + - + - + - Thermal Shutdown 2.5V + - Current Sense Reference Vref Vref ENA_1 FB1 ENA_1 FallingEdge Delay 0.95xVref FB2 Current Sense + - ENA_2 ENA_2 Vref VIN1 (2Pins) GND EN VIN2 (2Pins) SEQ (seeNoteB) PG1 MR2 RESET VIN1 MR1 VIN1 RisingEdge Deglitch Reset Comp VOUT2 (2Pins) FallingEdge Deglitch 0.83 x Vref FB2 V UVComp OUT2 FallingEdge Deglitch 0.83 x Vref FB1 V UVComp OUT1 Power Sequence Logic ENA_1 ENA_2 VIN1 10kW VSENSE1 (seeNoteA) V (2Pins) OUT1 VSENSE2 (seeNoteA) 10kW 0.95xVref FB1 RisingEdge Deglitch PG Comp + - TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Fixed Voltage Version A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the Application Information section. B. If the SEQ terminal is floating at the input, VOUT2 powers up first. Copyright © 2000–2007, Texas Instruments Incorporated Submit Documentation Feedback 7 |
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