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IDT71V632SA4PF Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT71V632SA4PF Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 19 page 6.42 7 IDT71V632, 64K x 32, 3.3V Synchronous SRAM with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges Operation(2) OE ZZ I/O Status Power Read L L Data Out (I/O0 - I/O31)Active Read H L High-Z Active Write X L High-Z — Data In (I/O0 - I/O31)Active Deselected X L High-Z Standby Sleep X H High-Z Sleep 3619 tbl 09 Operation GW BWE BW1 BW2 BW3 BW4 Read H H XX XX Read H L H H H H Write all Bytes L X X X X X Write all Bytes H L L L L L Write Byte 1(2) H L L HHH Write Byte 2(2) HL HL H H Write Byte 3(2) HL H H L H Write Byte 4(2) HL H H HL 3619 tbl 08 Linear Burst Sequence Table (LBO=VSS) Interleaved Burst Sequence Table (LBO=VDD) Asynchronous Truth Table(1) Synchronous Write Function Truth Table(1) NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Multiple bytes may be selected during the same cycle. NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 11 1 0 0 1 0 0 3619 tbl 10 Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 11 0 0 0 1 1 0 3619 tbl 11 |
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