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IDT71V632S8PF8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V632S8PF8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 19 page AUGUST 2001 DSC-3619/04 1 ©2000 Integrated Device Technology, Inc. Features x x x x x 64K x 32 memory configuration x x x x x Supports high system speed: Commercial: – A4 4.5ns clock access time (117 MHz) Commercial and Industrial: – 5 5ns clock access time (100 MHz) – 6 6ns clock access time (83 MHz) – 7 7ns clock access time (66 MHz) x x x x x Single-cycle deselect functionality (Compatible with Micron Part # MT58LC64K32D7LG-XX) x x x x x LBO input selects interleaved or linear burst mode x x x x x Self-timed write cycle with global write control ( GW), byte write enable ( BWE), and byte writes (BWx) x x x x x Power down controlled by ZZ input x x x x x Operates with a single 3.3V power supply (+10/-5%) x x x x x Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP). Description The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32 Pin Description Summary Pentium processor is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc. 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect IDT71V632 with full support of the Pentium™ and PowerPC™ processor interfaces. The pipelined burst architecture provides cost-effective 3-1-1-1 second- ary cache performance for processors up to 117MHz. The IDT71V632 SRAM contains write, data, address, and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V632 can provide four cycles of data for asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter accepts the first cycle address from the processor, initiating the access sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore it is available on the next rising clock edge. If burst mode operation is selected ( ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe availabletotheuseronthenextthreerisingclockedges.Theorderofthese three addresses will be defined by the internal burst counter and the LBO input pin. TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity in both desktop and notebook applications. A0–A15 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chips Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0–I/O31 Data Input/Output I/O Synchronous VDD, VDDQ 3.3V Power N/A VSS, VSSQ Array Ground, I/O Ground Power N/A 3619 tbl 01 |
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