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AR0135CS2M00SUEA0-DRBR1 Datasheet(PDF) 6 Page - ON Semiconductor |
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AR0135CS2M00SUEA0-DRBR1 Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 27 page AR0135CS www.onsemi.com 6 CONFIGURATION AND PINOUT The figures and tables below show a typical configuration for the AR0135CS image sensor and show the package pinouts. Figure 5. Serial 4-lane HiSPi Interface 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5 k W, but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The parallel interface output pads can be left unconnected if the serial output interface is used. 5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0135CS demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 7. Although 4 serial lanes are shown, the AR0135CS supports only 2- or 3-lane HiSPi. Notes: FLASH SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_P SLVS2_N VDD_PLL VDD_IO VAA VAA_PIX AGND DGND VAA_PIX VAA VDD_IO VDD SDATA SCLK EXTCLK OE_BAR RESET_BAR TEST To Controller From Controller Master Clock (6−50 MHz) Digital I/O Power1 Digital Core Power1 Analog Power1 Analog Power1 Analog Ground Digital Ground STANDBY VDD_SLVS HiSPi Power1 VDD_PLL PLL Power1 SLVS3_P SLVS3_N SLVSC_P SLVSC_N VDD VDD_SLVS |
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