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K7A403600B Datasheet(PDF) 3 Page - Samsung semiconductor |
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K7A403600B Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 18 page K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM - 3 - Rev 1.0 Nov 2001 K7A403200B K7A403600B 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM The K7A403600B, K7A403200B and K7A401800B are 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pen- tium and Power PC based System. It is organized as 128K(256K) words of 36(18) bits and inte- grates address and control registers, a 2-bit burst address counter and added some new functions for high perfor- mance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated inter- nally in the system ′s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(lin- ear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7A403600B, K7A403200B and K7A401800B are fab- ricated using SAMSUNG ′s high performance CMOS tech- nology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. GENERAL DESCRIPTION FEATURES LOGIC BLOCK DIAGRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Cont- nention ; 2cycle Enable, 1cycle Disable. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A . • Operating in commeical and industrial temperature range. CLK LBO ADV ADSC ADSP CS1 CS2 CS2 GW BW WEx OE ZZ DQa0 ~ DQd7 BURST CONTROL LOGIC BURST 128Kx36/32 , 256Kx18 ADDRESS CONTROL OUTPUT DATA-IN ADDRESS COUNTER MEMORY ARRAY REGISTER REGISTER BUFFER LOGIC A ′0~A′1 A0~A1 or A2~A17 A0~A16 REGISTER DQPa ~ DQPd or A0~A17 A2~A16 (x=a,b,c,d or a,b) or DQa0 ~ DQb7 DQPa ~ DQPb 36/32 or 18 FAST ACCESS TIMES PARAMETER Symbol -16 -14 Unit Cycle Time tCYC 6.0 7.2 ns Clock Access Time tCD 3.5 4.0 ns Output Enable Access Time tOE 3.5 4.0 ns |
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