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KAF-0261-AAA-CD-BA Datasheet(PDF) 9 Page - ON Semiconductor |
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KAF-0261-AAA-CD-BA Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 14 page KAF−0261 www.onsemi.com 9 OPERATION Table 9. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Voltage All Clocks –16 +16 V 1 Voltage OG 0 +8 V 2 Voltage VRD, VSS, VDD, GUARD 0 +20 V 2 Current Output Bias Current (IDD) 10 mA Capacitance 10 pF Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Voltage between any two clocks or between any clock and Vsub. 2. Voltage with respect to Vsub. WARNING: For maximum performance, built−in gate protection has been added only to the OG pin. These devices require extreme care during handling to prevent electrostatic discharge (ESD) induced damage. Devices are rated as Class 0 (<250 V per JESD22 Human Body Model test), or Class A (<200 V JESD22 Machine Model test). Table 10. DC BIAS OPERATING CONDITIONS Description Symbol Minimum Nominal Maximum Units Pin Impedance Substrate VSUB 0.0 0.0 0.0 V Common Output Amplifier Supply VDD 15.0 +17.0 17.5 V 5 pF, 2 KW (Note 1) Output Amplifier Return VSS 1.4 +2.0 2.1 V 5 pF, 2 KW Reset Drain VRD 11.5 +12 12.5 V 5 pF, 1 MW Output Gate OG 4.0 4.5 5.0 V 5 pF, 10 MW Guard Ring GUARD 9.0 +10.0 15.0 V 350 pF, 10 MW Load Gate VLG VSS − 1.0 VSS VSS + 1.0 V 1. Vdd = 17 volts for applications where the expected output voltage > 2.0 Volts. For applications where the expected useable output voltage is < 2 Volts Vdd can be reduced to 15 Volts. AC Operating Conditions Table 11. CLOCK LEVELS Description Symbol Level Minimum Nominal Maximum Units Pin Impedance Vertical Clock − Phase 1 fV1 Low −10.2 −10.0 −9.0 V 13 nF, 10 MW Vertical Clock − Phase 1 fV1 High 0.0 0 2.0 V Vertical Clock − Phase 2 fV2 Low −10.2 −10.0 −9.0 V 16 nF, 10 MW Vertical Clock − Phase 2 fV2 High 0.0 0 2.0 V Horizontal Clock − Phase 1 fH1 Low −2.2 −2.0 −1.8 V 160 pF, 10 MW Horizontal Clock − Phase 1 fH1 High 7.8 +8.0 8.2 V Horizontal Clock − Phase 2 fH2 Low −2.2 −2.0 −1.8 V 110 pF, 10 MW Horizontal Clock − Phase 2 fH2 High 7.8 +8.0 8.2 V Reset Clock fR Low 2.0 3.0 3.5 V 10 pF, 10 MW Reset Clock fR High 10.0 V |
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