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KAC-06040-CB-A-GEVK Datasheet(PDF) 6 Page - ON Semiconductor |
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KAC-06040-CB-A-GEVK Datasheet(HTML) 6 Page - ON Semiconductor |
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6 / 43 page  KAC−06040 www.onsemi.com 6 Pin Name Description E01 1DCLK+ E02 1DCLK− D01 1DATA0+ D02 1DATA0− C01 1DATA1+ C02 1DATA1− B01 1DATA2+ B02 1DATA2− A03 1DATA3+ B03 1DATA3− A04 1DATA4+ B04 1DATA4− A05 1DATA5+ B05 1DATA5− A06 1DATA6+ B06 1DATA6− Bank 1 LVDS Clock Bank 1 LVDS Data Pin Name Description C07 3DCLK+ C08 3DCLK− A07 3DATA0+ B07 3DATA0− A08 3DATA1+ B08 3DATA1− A09 3DATA2+ B09 3DATA2− A10 3DATA3+ B10 3DATA3− A11 3DATA4+ B11 3DATA4− A12 3DATA5+ B12 3DATA5− A13 3DATA6+ B13 3DATA6− Bank 3 LVDS Clock Bank 3 LVDS Data Pin Name Description C15 5DCLK+ C16 5DCLK− A15 5DATA0+ B15 5DATA0− A16 5DATA1+ B16 5DATA1− A17 5DATA2+ B17 5DATA2− A18 5DATA3+ B18 5DATA3− A19 5DATA4+ B19 5DATA4− A20 5DATA5+ B20 5DATA5− A21 5DATA6+ B21 5DATA6− Bank 5 LVDS Clock Bank 5 LVDS Data Pin Name Description A22 7DCLK+ B22 7DCLK− A23 7DATA0+ B23 7DATA0− A24 7DATA1+ B24 7DATA1− A25 7DATA2+ B25 7DATA2− B27 7DATA3+ B26 7DATA3− C27 7DATA4+ C26 7DATA4− D27 7DATA5+ D26 7DATA5− E27 7DATA6+ E26 7DATA6− Bank 7 LVDS Clock Bank 7 LVDS Data Pin Name Description AA01 0DCLK+ AA02 0DCLK− AB01 0DATA0+ AB02 0DATA0− AC01 0DATA1+ AC02 0DATA1− AD01 0DATA2+ AD02 0DATA2− AE03 0DATA3+ AD03 0DATA3− AE04 0DATA4+ AD04 0DATA4− AE05 0DATA5+ AD05 0DATA5− AE06 0DATA6+ AD06 0DATA6− Bank 0 LVDS Clock Bank 0 LVDS Data Pin Name Description AC07 2DCLK+ AC08 2DCLK− AE07 2DATA0+ AD07 2DATA0− AE08 2DATA1+ AD08 2DATA1− AE09 2DATA2+ AD09 2DATA2− AE10 2DATA3+ AD10 2DATA3− AE11 2DATA4+ AD11 2DATA4− AE12 2DATA5+ AD12 2DATA5− AE13 2DATA6+ AD13 2DATA6− Bank 2 LVDS Clock Bank 2 LVDS Data Pin Name Description AC15 4DCLK+ AC16 4DCLK− AE15 4DATA0+ AD15 4DATA0− AE16 4DATA1+ AD16 4DATA1− AE17 4DATA2+ AD17 4DATA2− AE18 4DATA3+ AD18 4DATA3− AE19 4DATA4+ AD19 4DATA4− AE20 4DATA5+ AD20 4DATA5− AE21 4DATA6+ AD21 4DATA6− Bank 4 LVDS Clock Bank 4 LVDS Data Pin Name Description AE22 6DCLK+ AD22 6DCLK− AE23 6DATA0+ AD23 6DATA0− AE24 6DATA1+ AD24 6DATA1− AE25 6DATA2+ AD25 6DATA2− AD26 6DATA3+ AD27 6DATA3− AC26 6DATA4+ AC27 6DATA4− AB26 6DATA5+ AB27 6DATA5− AA26 6DATA6+ AA27 6DATA6− Bank 6 LVDS Clock Bank 6 LVDS Data 1. All LVDS Data and Clock lines must be routed with 100 W differential transmission line traces. 2. All the traces for a single LVDS Bank should be the same physical length to minimize skew between the clock and data lines. 3. In 2 Bank mode, only LVDS banks 0 and 1 are active. 4. In 4 Bank mode, only LVDS bank 0, 1, 2, and 3 are active. 5. Float the pins of unused LVDS Banks to conserve power. 6. Unused pins in active banks (due to ADC bit depth < 14) are automatically tri-stated to save power, but these can also be floated. Table 6. LVDS PIN DESCRIPTION |
Similar Part No. - KAC-06040-CB-A-GEVK |
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Similar Description - KAC-06040-CB-A-GEVK |
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