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KAF-0261-AAA-CP-BA Datasheet(PDF) 10 Page - ON Semiconductor

Part # KAF-0261-AAA-CP-BA
Description  CCD Image Sensor
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

KAF-0261-AAA-CP-BA Datasheet(HTML) 10 Page - ON Semiconductor

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KAF−0261
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Table 12. AMPLIFIER SELECTION
Description
Symbol
Level
Using the High Gain
Output (Vout2)
Using the High Dynamic
Range Output (Vout1)
Units
Pin Impedance
Min
Nom
Max
Min
Nom
Max
Horizontal Clock −
Phase 1
fH21
Low
−4
fH2 low
fH2 low
fH2
V
10 pF, 10 MW
Horizontal Clock −
Phase 1
fH21
High
−4
fH2 low
fH2 low
fH2
V
Horizontal Clock −
Phase 2
fH22
Low
fH2
−4
fH2 low
fH2 low
V
10 pF, 10 MW
Horizontal Clock −
Phase 2
fH22
High
fH2
−4
fH2 low
fH2 low
V
1. When using Vout1 fH21 is clocked identically with fH2 while fH22 is held at a static level. When using Vout2 fH21 and fH22 are exchanged
so that fH22 is identical to fH2 and fH21 is held at a static level. The static level should be the same voltage as fH2 low.
2. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may require adjustments of these
voltages. Pins shown with impedances greater than 1 MW are expected resistances. These pins are only verified to 1 MW.
3. fV1, 2 capacitances are accumulated gate oxide capacitance, and so are an over-estimate of the capacitance.
4. This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult ON Semiconductor in
those situations in which operating conditions meet or exceed minimum or maximum levels.
Timing
Table 13. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
fH1, fH2 Clock Frequency
fH
5
8
MHz
1, 2, 3
V1, V2 Clock Frequency
fV
100
125
kHz
1, 2, 3
Pixel Period (1 Count)
tpix
125
200
ns
fH1, fH2 Set−up Time
tfHS
500
1000
ns
fV1, fV2 Clock Pulse Width
tfV
4
5
ms
2
Reset Clock Pulse Width
tfR
10
20
ns
4
Readout Time
treadout
40
64
ms
5
Integration Time
tint
6
Line Time
tline
78
122
ms
7
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Crossover of register clocks should be between 40−60% of
amplitude.
4. fR should be clocked continuously.
5. treadout = (520 * tline)
6. Integration time (tint) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot
noise.
7. tline = (3 * tfV) + tfHS + 530 * tpix + tpix


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