KAF−0261

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5

DEVICE DESCRIPTION

Pin Description and Device Orientation

Figure 4. Pinout Diagram

Pixel (1,1)

1

2

3

4

5

6

7

8

9

10

11

12

φR

VSS

φH21

φH2

VOUT1

OG

VDD1/VDD2

VOUT2

VRD

φH1

φH22

N/C

24

23

22

21

20

19

18

17

16

15

14

13

GUARD

SUB

SUB

VLG

Pixel (512,512)

Table 3. PIN DESCRIPTION

Pin

Name

Description

1

OG

Output Gate

2

VOUT2

Video Output from High Sensitivity Two−

Stage

3

VDD1 /

VDD2

Amplifier Supply for VOUT1 and VOUT2

Amplifiers

4

VRD

Reset Drain

5

fR

Reset Clock

6

VSS

Output Amplifier Return

7

fH1

Horizontal (Serial) CCD Clock − Phase 1

8

fH2

Horizontal (Serial) CCD Clock − Phase 2

9

VOUT1

Video Output from High Dynamic Range

Single−Stage Amplifier

10

fH21

Last Horizontal (Serial) CCD Phase −

Split Gate

11

fH22

Last Horizontal (Serial) CCD Phase −

Split Gate

12

N/C

No Connection

13

VSUB

Substrate

14

VSUB

Substrate

15

fV1

Vertical (Parallel) CCD Clock − Phase 1

16

fV1

Vertical (Parallel) CCD Clock − Phase 1

17

fV2

Vertical (Parallel) CCD Clock − Phase 2

18

fV2

Vertical (Parallel) CCD Clock − Phase 2

19

fV2

Vertical (Parallel) CCD Clock − Phase 2

20

fV2

Vertical (Parallel) CCD Clock − Phase 2

21

fV1

Vertical (Parallel) CCD Clock − Phase 1

22

fV1

Vertical (Parallel) CCD Clock − Phase 1

23

GUARD

Guard Ring

24

VLG

First Stage Load Transistor Gate for

Two−Stage

1. Pins 15, 16, 21, and 22 must be connected together − only one

Phase 1−clock driver is required.

2. Pins 17, 18, 19, and 20 must be connected together − only one

Phase 2−clock driver is required.