 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
M29DW640D90N6 Datasheet(PDF) 11 Page - STMicroelectronics |
|
||||||||||||||||||||||||||||||
M29DW640D90N6 Datasheet(HTML) 11 Page - STMicroelectronics |
|
|
11 / 55 page  11/56 M29DW640D SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state ma- chine. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A–1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the ad- dressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to in- clude this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. VPP/Write Protect (VPP/WP). The VPP/Write Protect pin provides two functions. The VPP func- tion allows the memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by by- passing the unlock cycles and/or using the multi- ple Word (2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands. The Write Protect function provides a hardware meth- od of protecting the four outermost boot blocks (two at the top, and two at the bottom of the ad- dress space). When VPP/Write Protect is Low, VIL, the memory protects the four outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the four outermost boot blocks (two at the top, and two at the bottom of the address space). Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. When VPP/Write Protect is raised to VPP the mem- ory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL nor- mal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 18. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreli- able. A 0.1µF capacitor should be connected be- tween the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if VPP/WP is at VIL, then the four outer- most boot blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 19 and Figure 17., Reset/ Block Temporary Unprotect AC Waveforms. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. |
Similar Part No. - M29DW640D90N6 |
|
Similar Description - M29DW640D90N6 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
