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TPS92661QPHPRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS92661QPHPRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 53 page  6 TPS92661-Q1 SLUSBU2A – SEPTEMBER 2014 – REVISED FEBRUARY 2016 www.ti.com Product Folder Links: TPS92661-Q1 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) Single channel on-resitance (RDS(on)) measurement includes internal bond wires. All switches on-resistance (RALL(on)) should be used for all power calculations. See Internal Switch Resistance for details. (2) Specified by design. Not production tested. 6.5 Electrical Characteristics Limits apply over operating junction temperature range –40°C ≤ TJ ≤ +150°C. Typical values represent the most likely parametric norm at TJ = 25°C. Unless otherwise noted, VIN = 5 V. For digital outputs, CLOAD = 20 pF. PARAMETER CONDITIONS MIN TYP MAX UNIT GENERAL IVIN-OP Input operating bias current No switching 1 mA VIN-UVT VIN internal POR threshold VIN rising 4.5 V VCC-REG Regulated VCC voltage 0 mA ≤ IVCC ≤ 5 mA 3.1 3.3 3.5 V IVCC-LIM VCC current limit 10 mA VCPP Charge pump operating voltage VVIN = 5 V, 0 V ≤ VSW ≤ –60 V 6.2 V fCPP Charge pump oscillator frequency 1.3 2.3 3.3 MHz LED MATRIX SWITCHES RDS(on) LED switch on-resistance (1) 225 m Ω RALL(on) All switches on-resistance Measured LED12 - LED0 1800 3400 m Ω IDS(off) OFF state switch leakage current 50 µA VTH-S LED short threshold voltage 0 V ≤ VSW ≤ –60 V 0.52 1.4 V VTH-O LED OPEN threshold voltage 0 V ≤ VSW ≤ –60 V 5 6 6.9 V tTO-O LED OPEN detection and correction delay 50 150 ns tREP LED fault reporting delay 5 µs tRISE(LEDx) LEDx drain voltage rise time(2) ILED = 800 mA 2 µs tFALL(LEDx) LEDx drain voltage fall time(2) ILED = 800 mA 2 µs DIGITAL SPECIFICATIONS VIH-TH High-level input voltage threshold 1.9 V VIL-TH Low-level input voltage threshold 0.8 V VOH High-level output voltage ISOURCE = 2 mA, VVCC = 4.0 V 4.27 V VOL Low-level output voltage ISINK = 2 mA, VVCC = 4.5 V 0.23 V IOS Output short circuit current (source or sink) VVCC = 4.5 V 42 mA RSP Internal SYNC pull-down 100 k Ω tWD-TO CLK watchdog timeout 32/fCPP µs tTO CLK rise to TX output valid(2) 80 ns tTZ CLK rise to TX output tri-state(2) 80 ns |
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