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TLS850D0TAV33 Datasheet(PDF) 6 Page - Infineon Technologies AG |
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TLS850D0TAV33 Datasheet(HTML) 6 Page - Infineon Technologies AG |
6 / 31 page Data Sheet 6 Rev. 1.0, 2015-12-01 TLS850D0TA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment TLS850D0TAV50 and TLS850D0TAV33 Figure 3 Pin Configuration 3.2 Pin Definitions and Functions TLS850D0TAV50 and TLS850D0TAV33 Pin Symbol Function 1I Input It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close to the IC terminals, in order to compensate line influences. See also Chapter 6.2.1 2EN Enable (integrated pull-down resistor) Enable the IC with high level input signal; Disable the IC with low level input signal; 3RO Reset Output (intergrated pull-up resistor to Q) Open collector output; Leave open if the reset function is not needed 4GND Ground 5RADJ Reset Threshold Adjustment Connect to GND to use standard value; Connect an external voltage divider to adjust reset threshold 6DT Delay Timing (integrated pull-down resistor) Connect to GND or Q to select Reset timing acc. to Table 8 7Q Output Voltage Connect output capacitor C Q to GND close to the IC’s terminals, respecting the values specified for its capacitance and ESR in “Functional Range” on Page 8 Heat Slug – Heat Slug Connect to heatsink area; Connect to GND 12 3 4 5 7 6 |
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