Detailed Description

The MAX9374/MAX9374A are 2.0GHz differential

LVPECL-to-LVDS translators. The output is differential

LVDS and conforms to the ANSI TIA/EIA-644 LVDS

standard. The inputs are biased with internal resistors

such that the output is differential low when inputs are

single-ended input operation. The MAX9374 is

designed for low-voltage operation from 2.375V to

2.625V in systems with a nominal 2.5V supply. The

MAX9374A is designed for 3.0V to 3.6V operation in

systems with a nominal 3.3V supply.

Differential LVPECL Input

The MAX9374/MAX9374A accept differential LVPECL

inputs and can be configured to accept single-ended

put. The maximum magnitude of the differential signal

This limit also applies to the difference between any ref-

erence voltage input and a single-ended input.

Specifications for the high and low voltages of a differ-

The differential inputs can be configured to accept a

ence voltage. A noninverting, single-ended input is pro-

single-ended input signal to the D input. Similarly, an

input and applying the input signal to the D input. With

a differential input configured as single ended (using

GND or with a single-ended LVPECL signal. Note that a

differential input of at least 95mV to switch the outputs

Characteristics table.

Input Bias Resistors

Internal biasing resistors ensure a (differential) output-

low condition in the event that the inputs are not connect-

ed. The inverting input (D) is biased with a 36.5k

Ω pull-

Ω pullup to GND. The

noninverting input (D) is biased with a 75k

Ω pullup to

Ω pulldown to GND.

Differential LVDS Output

The differential outputs conform to the ANSI TIA/EIA-644

LVDS standard. Typically, terminate the outputs with 100

Ω

across Q and Q, as shown in the Typical Application

Circuit. The outputs are short-circuit protected.

Applications Information

Supply Bypassing

ceramic 0.1µF and 0.01µF capacitors in parallel and as

close to the device as possible, with the 0.01µF capaci-

tor closest to the device. Use multiple parallel vias to

erence output, bypass it with a 0.01µF ceramic capaci-

left open).

Controlled-Impedance Traces

Input and output trace characteristics affect the perfor-

mance of the MAX9374/MAX9374A. Connect high-fre-

quency input and output signals to 50

Ω characteristic

impedance traces. Minimize the number of vias to pre-

vent impedance discontinuities. Reduce reflections by

maintaining the 50

Ω characteristic impedance through

cables and connectors. Reduce skew within a differen-

tial pair by matching the electrical length of the traces.

Output Termination

Terminate the outputs with 100

Ω across Q and Q as

shown in the Typical Application Circuit. Both outputs

must be terminated.

Differential LVPECL-to-LVDS Translators

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