KAI-29050-AXA-JR-B2 datasheet(7/33 Pages) ONSEMI

Part #	KAI-29050-AXA-JR-B2

Description	Interline CCD Image Sensor

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Manufacturer	ONSEMI [ON Semiconductor]

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KAI−29050

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Table 5. PIN DESCRIPTION

Name

Description

1

V3B

Vertical CCD Clock, Phase 3, Bottom

3

V1B

Vertical CCD Clock, Phase 1, Bottom

4

V4B

Vertical CCD Clock, Phase 4, Bottom

5

VDDa

Output Amplifier Supply, Quadrant a

6

V2B

Vertical CCD Clock, Phase 2, Bottom

7

GND

Ground

8

VOUTa

Video Output, Quadrant a

9

Ra

Reset Gate, Quadrant a

10

RDa

Reset Drain, Quadrant a

11

H2SLa

Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant a

12

OGa

Output Gate, Quadrant a

13

H1Ba

Horizontal CCD Clock, Phase 1, Barrier,

Quadrant a

14

H2Ba

Horizontal CCD Clock, Phase 2, Barrier,

Quadrant a

15

H2Sa

Horizontal CCD Clock, Phase 2,

Storage, Quadrant a

16

H1Sa

Horizontal CCD Clock, Phase 1,

Storage, Quadrant a

17

SUB

Substrate

18

FDGab

Fast Line Dump Gate, Bottom

19

N/C

No Connect

20

FDGab

Fast Line Dump Gate, Bottom

21

H2Sb

Horizontal CCD Clock, Phase 2,

Storage, Quadrant b

22

H1Sb

Horizontal CCD Clock, Phase 1,

Storage, Quadrant b

23

H1Bb

Horizontal CCD Clock, Phase 1, Barrier,

Quadrant b

24

H2Bb

Horizontal CCD Clock, Phase 2, Barrier,

Quadrant b

25

H2SLb

Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant b

26

OGb

Output Gate, Quadrant b

27

Rb

Reset Gate, Quadrant b

28

RDb

Reset Drain, Quadrant b

29

GND

Ground

30

VOUTb

Video Output, Quadrant b

31

VDDb

Output Amplifier Supply, Quadrant b

32

V2B

Vertical CCD Clock, Phase 2, Bottom

33

V1B

Vertical CCD Clock, Phase 1, Bottom

34

V4B

Vertical CCD Clock, Phase 4, Bottom

35

V3B

Vertical CCD Clock, Phase 3, Bottom

36

ESD

ESD Protection Disable

Name

Description

72

ESD

ESD Protection Disable

71

V3T

Vertical CCD Clock, Phase 3, Top

70

V4T

Vertical CCD Clock, Phase 4, Top

69

V1T

Vertical CCD Clock, Phase 1, Top

68

V2T

Vertical CCD Clock, Phase 2, Top

67

VDDc

Output Amplifier Supply, Quadrant c

66

VOUTc

Video Output, Quadrant c

65

GND

Ground

64

RDc

Reset Drain, Quadrant c

63

Rc

Reset Gate, Quadrant c

62

OGc

Output Gate, Quadrant c

61

H2SLc

Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant c

60

H2Bc

Horizontal CCD Clock, Phase 2, Barrier,

Quadrant c

59

H1Bc

Horizontal CCD Clock, Phase 1, Barrier,

Quadrant c

58

H1Sc

Horizontal CCD Clock, Phase 1,

Storage, Quadrant c

57

H2Sc

Horizontal CCD Clock, Phase 2,

Storage, Quadrant c

56

FDGcd

Fast Line Dump Gate, Top

55

N/C

No Connect

54

FDGcd

Fast Line Dump Gate, Top

53

SUB

Substrate

52

H1Sd

Horizontal CCD Clock, Phase 1,

Storage, Quadrant d

51

H2Sd

Horizontal CCD Clock, Phase 2,

Storage, Quadrant d

50

H2Bd

Horizontal CCD Clock, Phase 2, Barrier,

Quadrant d

49

H1Bd

Horizontal CCD Clock, Phase 1, Barrier,

Quadrant d

48

OGd

Output Gate, Quadrant d

47

H2SLd

Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant d

46

RDd

Reset Drain, Quadrant d

45

Rd

Reset Gate, Quadrant d

44

VOUTd

Video Output, Quadrant d

43

GND

Ground

42

V2T

Vertical CCD Clock, Phase 2, Top

41

VDDd

Output Amplifier Supply, Quadrant d

40

V4T

Vertical CCD Clock, Phase 4, Top

39

V1T

Vertical CCD Clock, Phase 1, Top

38

DevID

Device Identification

37

V3T

Vertical CCD Clock, Phase 3, Top

1. Liked named pins are internally connected and should have a

common drive signal.

2. N/C pins (19, 55) should be left floating.

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