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NOIP1SN5000A Datasheet(PDF) 4 Page - ON Semiconductor |
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NOIP1SN5000A Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 75 page NOIP1SN5000A www.onsemi.com 4 Table 5. ELECTRICAL SPECIFICATIONS Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9) Parameter Description Min Typ Max Units Power Supply Parameters − P1 − SN/SE/FN (ZROT) (Note: All ground pins (gnd_18, gnd_33 and gnd_colpc) should be connected to an external 0 V ground reference.) vdd_33 Supply voltage, 3.3 V 3.2 3.3 3.4 V Idd_33 Current consumption 3.3 V supply 355 mA vdd_18 Supply voltage, 1.8 V 1.7 1.8 1.9 V Idd_18 Current consumption 1.8 V supply 140 mA vdd_pix Supply voltage, pixel 3.25 3.3 3.35 V Idd_pix Current consumption pixel supply 10 mA Ptot Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V 1.45 W Pstby_lp Power consumption in low power standby mode 50 mW Popt Power consumption at lower pixel rates Configurable Power Supply Parameters − P3 − SN/SE/FN (NZROT) (Note: All ground pins (gnd_18, gnd_33 and gnd_colpc) should be connected to an external 0 V ground reference.) vdd_33 Supply voltage, 3.3 V 3.2 3.3 3.4 V Idd_33 Current consumption 3.3 V supply (4/2/1 LVDS) 215 mA vdd_18 Supply voltage, 1.8 V 1.7 1.8 1.9 V Idd_18 Current consumption 1.8 V supply (4/2/1 LVDS) 105 mA vdd_pix Supply voltage, pixel 3.25 3.3 3.35 V Idd_pix Current consumption pixel supply (4/2/1 LVDS) 5 mA Ptot Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V P3, 4 LVDS, NZROT P3, 2 LVDS, NZROT P3, 1 LVDS, NZROT 915 520 370 mW Pstby_lp Power consumption in low power standby mode 50 mW Popt Power consumption at lower pixel rates Configurable I/O − P1,P3 − SN/SE/FN (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed fserdata Data rate on data channels DDR signaling − 4 data channels, 1 synchronization channel 720 Mbps fserclock Clock rate of output clock Clock output for mesochronous signaling 360 MHz Vicm LVDS input common mode level 0.3 1.25 1.8 V Tccsk Channel to channel skew (Training pattern should be used to correct per channel skew) 50 ps Electrical Interface − P1,P3 − SN/SE/FN fin Input clock rate when PLL used 72 MHz fin Input clock when LVDS input used 360 MHz tidc Input clock duty cycle when PLL used 45 50 55 % tj Input clock jitter 20 ps fspi SPI clock rate when PLL used at fin = 72 MHz 10 MHz ratspi (=fin/fspi) 10−bit (8 LVDS channels), PLL used (fin = 72 MHz) − P1 only 6 10−bit (4 LVDS channels), PLL used (fin = 72 MHz) 12 10−bit (2 LVDS channels), PLL used (fin = 72 MHz) 24 10−bit (1 LVDS channel), PLL used (fin = 72 MHz) 48 10−bit (8 LVDS channels), LVDS input used (fin = 360 MHz) 30 10−bit (4 LVDS channels), LVDS input used (fin = 360 MHz) 60 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. All parameters are characterized for DC conditions after thermal equilibrium is established. 6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. Minimum and maximum limits are guaranteed through test and design. 8. Refer to ACSPYTHON5000 available at CISP extranet for detailed acceptance criteria specifications. 9. For power supply management recommendations, please refer to Application Note AND9158. |
Similar Part No. - NOIP1SN5000A_16 |
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