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NOIP1FN1300A-QDI Datasheet(PDF) 11 Page - ON Semiconductor |
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NOIP1FN1300A-QDI Datasheet(HTML) 11 Page - ON Semiconductor |
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11 / 75 page  NOIP1SN1300A www.onsemi.com 11 OVERVIEW Figures 9 and 10 give an overview of the major functional blocks of the P1, P3 − SN/SE/FN and P2−SN/SE sensor respectively. Figure 9. Block Diagram − P1, P3 − SN/SE/FN Pixel Array Analog Front End (AFE) Data Formatting Serializers & LVDS Interface LVDS Clock Input 4, 2, 1 Multiplexed LVDS Output Channels 1 LVDS Sync Channel 1 LVDS Clock Channel 8 analog channels 8 x 10 bit digital channels 4 x 10 bit digital channels Column Structure Image Core Bias Image Core Automatic Exposure Control (AEC) Clock Distribution CMOS Clock Input LVDS Receiver PLL Control & Registers Analog Front End (AFE) Data Formatting Output MUX CMOS Interface 8 analog channels 8 x 10 bit digital channels 10 bit Parallel Data Frame Valid Indication Line Valid Indication 4 x 10 bit digital channels Column Structure Image Core Bias Image Core PLL Figure 10. Block Diagram − P2−SN/SE CMOS Clock Clock Distribution CMOS Clock Input Automatic Exposure Control (AEC) Control & Registers Pixel Array Note: P3 part only has 2,1 Multiplexed LVDS Output Channels Image Core The image core consists of: • Pixel Array • Address Decoders and Row Drivers • Pixel Biasing The PYTHON 1300 pixel array contains 1280 (H) x 1024 (V) readable pixels with a pixel pitch of 4.8 mm. The PYTHON 300 and PYTHON 500 image arrays contain 672 (H) x 512 (V) and 832 (H) x 632 (V) readable pixels respectively, inclusive of 16 pixel rows and 16 pixel columns at every side to allow for reprocessing or color reconstruction. The sensors use in−pixel CDS architecture, which makes it possible to achieve a low noise read out of the pixel array in global shutter mode with CDS. The function of the row drivers is to access the image array line by line, or all lines together, to reset or read the pixel data. The row drivers are controlled by the on−chip sequencer and can access the pixel array. The pixel biasing block guarantees that the data on a pixel is transferred properly to the column multiplexer when the row drivers select a pixel line for readout. Phase Locked Loop The PLL accepts a (low speed) clock and generates the required high speed clock. Optionally this PLL can be bypassed. Typical input clock frequency is 72 MHz. LVDS Clock Receiver The LVDS clock receiver receives an LVDS clock signal and distributes the required clocks to the sensor. Typical input clock frequency is 360 MHz in 10−bit mode and 288 MHz in 8−bit mode. The clock input needs to be terminated with a 100 W resistor. Column Multiplexer All pixels of one image row are stored in the column sample−and−hold (S/H) stages. These stages store both the reset and integrated signal levels. The data stored in the column S/H stages is read out through 8 parallel differential outputs operating at a frequency of 36 MHz. At this stage, the reset signal and integrated signal values are transferred into an FPN−corrected differential signal. A programmable gain of 1x, 2x, or 4x can be applied to the signal. The column multiplexer also supports read−1−skip−1 and read−2−skip−2 mode. Enabling this mode increases the frame rate, with a decrease in resolution. |
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