NJ8821

4

PHASE COMPARATORS

The digital phase/frequency detector drives a three-state

output, PDB, which provides a ‘coarse’ error signal to enable

fast switching between channels. The PDB output is active

until the phase error is within the sample and hold phase

detector, PDA, window, when PDB becomes high impedance.

Phase-lock is indicated at this point by a low level on LD. The

sample and hold phase detector provides a ‘fine’ error signal

to give further phase adjustment and to hold the loop in lock.

An internally generated ramp, controlled by the digital

output from both the reference and main divider chains, is

sampled at the reference frequency to give the ‘fine’ error

signal, PDA. When in phase lock, this output would be typically

to phase error. The relationship between this offset and the

phase error is the phase comparator gain, which is

programmable with an external resistor, RB. An internal 50pF

capacitor is used in the sample and hold comparator.

CRYSTAL OSCILLATOR

When using the internal oscillator, the stability may be

enhanced at high frequencies by the inclusion of a resistor

between pin 8 (OSC OUT) and the other components. A value

of 150-270

Ω is advised.

PROGRAMMING/POWER UP

Data and signal input pins should not have input applied to

occur.

10ms. If shorter lock-up times are are required when making

only small changes in frequency, the GPS NJ8823 (with non-

resettable counters) should be considered.

DS2

0

0

0

0

1

1

1

1

WORD

1

2

3

4

5

6

7

8

DS1

0

0

1

1

0

0

1

1

DS0

0

1

0

1

0

1

0

1

D3

M1

M5

M9

A3

-

R3

R7

-

D2

M0

M4

M8

A2

A6

R2

R6

R10

D1

-

M3

M7

A1

A5

R1

R5

R9

D0

-

M2

M6

A0

A4

R0

R4

R8

Fig. 5 Data map

Fig. 6 Timing diagram

PROGRAMMING

Timing is generated externally, normally from a

microprocessor, and allows the user to change the data in

selected latches as defined by the data map Fig.5. The PE pin

is used as a strobe for the data: taking PE high causes data to

be transferred from the data pins (D0-D3) into the addressed

latch. Following the falling edge of PE, the data is retained in

the addressed latch and the data inputs are disabled. Data

transfer from all internal latches into the counters occurs

simultaneously with the transfer of data into latch 1, which

would therefore normally be the last latch addressed during

each channel change. Timing information for this mode of

operation is given in Fig. 6.

When re-programming, a reset to zero state is followed by

reloading with the new counter values. This means that the

synthesiser loop lock-up time is well defined and less than

DS0-DS2

PE

D0 - D3