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IS25LP080D-JBLE1 Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS25LP080D-JBLE1 Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
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10 / 108 page  IS25LP080D IS25WP080D/040D/020D Integrated Silicon Solution, Inc.- www.issi.com 10 Rev. A 09/02/2016 4. SPI MODES DESCRIPTION Multiple IS25LP080D device or multiple IS25WP080D/040D/020D devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure 4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK. Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices) Notes: 1. According to the P7 bit setting in Read Register, either HOLD# (P7=0) or RESET# (P7=1) pin can be selected. 2. SI and SO pins become bidirectional IO0 and IO1 respectively during Dual I/O mode and SI, SO, WP#, and HOLD# pins become bidirectional IO0, IO1, IO2, and IO3 respectively during Quad I/O or QPI mode. SPI interface with (0,0) or (1,1) SPI Master (i.e. Microcontroller) SPI Memory Device SPI Memory Device SPI Memory Device SCK SO SI SCK SDI SDO CE# WP# HOLD# or RESET SCK SO SI CE# WP# HOLD# or RESET# SCK SO SI CE# WP# CS3 CS2 CS1 HOLD# or RESET# (1) (1) (1) |
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