Dual DMOS Full-Bridge Motor Driver

A3916

8

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

not enabled until the source driver is turned off and the cross-

over delay has expired. This feature helps lower the voltage drop

during current recirculation, lowering power dissipation in the

bridge.

OCP

If an overcurrent event occurs, both motor bridges are disabled

until either SLEEPn is brought low or the VBB supply is cycled.

FAULTn

This is an open-drain output that is pulled low during a TSD

or overcurrent event. The output is released when the die tem-

perature falls below the TSD level minus the hysteresis. For an

over-current event, the output is held low until either SLEEPn is

brought low or the VBB supply is cycled.

Parallel Operation

The A3916 can be paralleled for applications that require higher

output currents. In paralleled mode, the driver can source 1.8 A

continuous. The A3916 has two completely independent bridges

with separate overcurrent latches. This allows the device to

supply two separate loads, and as a result, when paralleled, it is

imperative that the internal current control is disabled by shorting

the sense pins to ground.

Because the overcurrent trip threshold is internally fixed at 0.2 V,

the trace resistance must be kept small so the internal current

latch is not triggered prematurely. With acceptable margin, the

voltage drop across the trace resistance should be under 0.1 V. At

a peak current of 2.5 A, the trace resistance should be kept below

40 mΩ to prevent false tripping of the overcurrent latch.

Each bridge has some variation in propagation delay. During this

time, it is possible that one bridge will have to support the full

load current for a very short period of time. Propagation delays

are characterized and guard banded to protect the driver from

damage during these events.