CAT34TS02

http://onsemi.com

3

Symbol

Parameter

Conditions

Max

Units

(Note 4)

SDA, EVENT Pin Capacitance

8

pF

Input Capacitance (other pins)

6

(Note 5)

Address Input Current (A0, A1, A2)

Product Rev C

35

mA

2

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

5. When not driven, the A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively

strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,

Symbol

Parameter

Min

Max

Units

Clock Frequency

10

400

kHz

High Period of SCL Clock

600

ns

Low Period of SCL Clock

1300

ns

SMBus SCL Clock Low Timeout

25

35

ms

SDA and SCL Rise Time

300

ns

SDA and SCL Fall Time

300

ns

Data Setup Time

100

ns

START Condition Setup Time

600

ns

START Condition Hold Time

600

ns

STOP Condition Setup Time

600

ns

Bus Free Time Between STOP and START

1300

ns

Input Data Hold Time

0

ns

Output Data Hold Time

200

900

ns

Noise Pulse Filtered at SCL and SDA Inputs

100

ns

Write Cycle Time

5

ms

Power−up Delay to Valid Temperature Recording

100

ms

The time−out count−down is activated in the interval between START and STOP when SCL is low and is reset while SCL is high. The minimum

clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD component

is DC, while the minimum operating frequency for the TS component is limited only by the SMBus time−out. For the CAT34TS02 Rev. C,

both the TS and the SPD implement the time−out feature.