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CS51031GDR8G Datasheet(PDF) 4 Page - ON Semiconductor |
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CS51031GDR8G Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 10 page CS51031 http://onsemi.com 4 Q Q Q Q RG VC VGATE PGND R S F2 VGATE Flip−Flop G2 + − VFB Comparator A6 VFB 1.25 V G1 0.7 V Hold Off Comp Fault Comp 1.15 V A4 CS Charge Sense Comparator R S F1 Slow Discharge Flip−Flop GND G4 G5 − + A3 Slow Discharge Comparator 2.3 V 2.4 V + − A2 CS Comparator 2.5 V 1.5 V IT 55 IT 5 IT CS G3 VREF = 3.3 V COSC 2.5 V 1.5 V A1 VREF 3.3 V VCCOK VCC Oscillator Comparator VCC VREF IC 7IC Figure 2. Block Diagram CIRCUIT DESCRIPTION THEORY OF OPERATION Control Scheme The CS51031 monitors the output voltage to determine when to turn on the P−Ch FET. If VFB falls below the internal reference voltage of 1.25 V during the oscillator’s charge cycle, the P−Ch FET is turned on and remains on for the duration of the charge time. The P−Ch FET gets turned off and remains off during the oscillator’s discharge time with the maximum duty cycle to 80%. It requires 7.0 mV typical, and 20 mV maximum ripple on the VFB pin is required to operate. This method of control does not require any loop stability compensation. |
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