BR25H160F-2LB

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Datasheet

Datasheet

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TSZ22111・15・001

TSZ02201-0R1R0G100340-1-2

27.Feb.2014 Rev.002

Serial Input / output Timing

Block diagram

Figure 5. Block diagram

Figure 2. Input timing

SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB.

Figure 3. Input / Output timing

SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB.

Figure 4. HOLD timing

SO

INSTRUCTION DECODE

CONTROL CLOCK

GENERATION

VOLTAGE

DETECTION

WRITE

INHIBITION

HIGH VOLTAGE

GENERATOR

INSTRUCTION

REGISTER

16K

EEPROM

ADDRESS

REGISTER

DATA

REGISTER

ADDRESS

DECODER

READ/WRITE

AMP

8bit

8bit

STATUS REGISTER

CSB

SCK

HOLDB

11bit

11bit

WPB

SI

CSB

SCK

SI

SO

tCS

tCSS

tSCKS

tSCKWL

tSCKWH

tDIS

tDIH

tRC

tFC

High-Z

CSB

SCK

SI

SO

tPD

tOH

tRO,tFO

tOZ

tCSH

tSCKH

tCS

High-Z

CSB

SCK

SI

n+1

"H"

"L"

n

Dn

n-1

Dn

Dn-1

HOLDB

SO

Dn+1

tHFS

tHFH

tHOZ

tHRS tHRH

tDIS

tHPD

High-Z